Arty Z7: APSoC Zynq-7000 Entwicklungsboard für Maker und Hobbyisten

Preview: Arty Z7: APSoC Zynq-7000 Z7-10 Development Board for Makers and Hobbyists

Arty Z7: APSoC Zynq-7000 Z7-10 Development Board for Makers and Hobbyists

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Order number: 28018
In Stock: 19
Standard leadtime (weeks): 5

The Arty Z7 is a ready-to-use development platform designed around the Zynq-7000 All... more

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Product information "Arty Z7: APSoC Zynq-7000 Z7-10 Development Board for Makers and Hobbyists"

The Arty Z7 is a ready-to-use development platform designed around the Zynq-7000 All Programmable System-on-Chip (AP SoC) from Xilinx. The Zynq-7000 architecture tightly integrates a dual-core, 650 MHz ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. This pairing grants the ability to surround a powerful processor with a unique set of software defined peripherals and controllers, tailored by you for whatever application is being conquered. The design process is very straightforward and provides a systematic path between defining your custom peripheral set and bringing it's functionality up to a Linux OS running on the processor. Digilent provides a number of materials and resources for the Arty Z7 that will get you up and running with this process quickly.

Digilent products are warranted to be free from manufacturing defects for 30 days from the date of purchase. No other express or implied warranties are provided.

Key Features

	Arty Z7-10
FPGA part	XC7Z010-1CLG400C
1 MSPS On-chip ADC	Yes
Processor	Dual ARM Cortex A9
Look-up Tables (LUTs)	17,600
Flip-flops	35,200
Block RAM	270 KB
Clock Management Tiles	2
Available Shield I/O	26

ZYNQ Processor
- 650MHz dual-core Cortex-A9 processor
- DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
- High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
- Low-bandwidth peripheral controller: SPI, UART, CAN, I2C
- Programmable from JTAG, Quad-SPI flash, and microSD card
- Programmable logic equivalent to Artix-7 FPGA
Memory
- 512MB DDR3 with 16-bit bus @ 1050Mbps
- 16MB Quad-SPI Flash with factory programmed 48-bit globally unique EUI-48/64™ compatible identifier
- microSD slot
Power
- Powered from USB or any 7V-15V external power source
USB and Ethernet
- Gigabit Ethernet PHY
- USB-JTAG Programming circuitry
- USB-UART bridge
- USB OTG PHY (supports host only)
Audio and Video
- HDMI sink port (input)
- HDMI source port (output)
- PWM driven mono audio output with 3.5mm jack
Switches, Push-buttons, and LEDs
- 4 push-buttons
- 2 slide switches
- 4 LEDs
- 2 RGB LEDs
Expansion Connectors
- Two standard Pmod ports
- 16 Total FPGA I/O
Arduino/chipKIT Shield connector
- Up to 49 Total FPGA I/O (see table below)
- 6 Single-ended 0-3.3V Analog inputs to XADC
- 4 Differential 0-1.0V Analog inputs to XADC

Associated Pmods

Overview Pmods by Digilent Inc. sorted after their name, Bus, logic level and specification version.

Pmods are designed to plug directly into Pmod host ports that adhere to the Digilent Pmod Interface Specification. Additionally, the Digilent Pmod Standard lays out guidelines for form factor, communication protocols and access to a target audience through reference manuals, code examples, user guides, and technical support.

Getting started with Digilent Pmod IPs

Scope of Delivery

1 x Arty Z7-10 in a Digilent cardboard packaging with protective foam

References

Manufacturer: Digilent Inc.
Manufacturer's article name: Arty Z7: APSoC Zynq-7000 Development Board for Makers and Hobbyists
Manufacturer's article number: 410-346-10

Resources

Other Digilent products are available on request.

Related links to "Arty Z7: APSoC Zynq-7000 Z7-10 Development Board for Makers and Hobbyists"

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

Digilent
OHO-Elektronik
SunDance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

Key Features

Associated Pmods

Scope of Delivery

References

Resources

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CR00100 Basic Example

CR00100 Basic Example

CR00103 Certus Test

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0950 Basic Linux Example

TEI0022 Basic Example

TEI0022 Basic Example

TE0717 Hello World Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0003 LED Sequencer Example

TEI0003 NIOS SDRAM Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEM0001 Test Board Example

TEI0050 Basic Example

TEI0015 DAQ Capture Demo

TEI0015 Data Capture Demo

TEI0015 Jupyter Demo

TEI0016 DAQ Capture Demo

TEI0016 Data Capture Demo

TEI0016 Jupyter Demo

TEI0023 DAQ Capture Demo

TEI0023 Data Capture Demo

TEI0023 Jupyter Demo

TE0890 Hello World Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

Basic Linux Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

TEM0005 Webserver Demo1

MicroBlaze Basic-System

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725LP Frequency Measurement

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0714 VIO LED Design

TE0714 Basic Barmetal Example

TE0763 Hello World Example

TE0710 MicroBlaze System

TE0710 UNIO MAC

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0711 F32C Demo Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0712 MicroBlaze Basic-System

TE0712 Basic Linux Example

TE0712 Basic Linux Example