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TE0720 Ethernet Design for TE0706 Carrier Board


-Downloadable files are located below the description-

Short Description:
Zynq-PS with basic-IOs and RGMII for second Ethernet PHY on TE0706.
Excerpt of special Block-Design components/interfaces:
Component Description
PS-MIOs activated:SPI0, SPI1, I2C0, UAR0, UART1, GPIO, SD0, SD1, USB0, ENET0,ENET1, QSPI
Xilinx-IP GMII to RGMII
TE-IP TE0720 System-Controller
Additional software application for SDK/HSI and Linux:
Application Description
zynq_fsbl Zynq First Stage Bootloader (Modified)
hello_world Xilinx Hello World Example
u-boot Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default)
Additional sources:
Name Folder Description
PetaLinux Project <design_name>/os/petalinux PetaLinux Project with Ethernet,USB,RTC
Additional prebuilt-content (larger ZIP-file):
File File-Extension Description
Bin-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File *.bit FPGA Configuration File
Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files *.hdf Exported Vivado Hardware Specification for SDK/HSI
BIF-File *.bif File with description to generate Bin-File
OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Diverse Reports -- Report files in different formats
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Files te0720-TE0706_ETH-vivado_2016.2-build_08_20161206155111.zip
Size 37,49 MB / Modified 06.12.2016 - 15:51:14
te0720-TE0706_ETH_noprebuilt-vivado_2016.2-build_08_20161206155126.zip
Size 4,28 MB / Modified 06.12.2016 - 15:51:28