FPGA-Modul mit Xilinx Artix-7 XC7A15T-1CSG324C 2 x 50 Pin mit 2,54 mm Raster

Preview: FPGA Module with AMD Artix™ 7A15T-1C, 2 x 50 Pin-Header, 3,5 x 7,3 cm

FPGA Module with AMD Artix™ 7A15T-1C, 2 x 50 Pin-Header, 3,5 x 7,3 cm

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€79.00 (94.01 € gross) *

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Order number: TE0725-03-15-1C
In Stock: 0
Article status: Upgrade available

Quantity	Unit price
To 9	€79.00 (94.01 € gross) *
From 10	€71.10 (84.61 € gross) *
From 25	€67.15 (79.91 € gross) *
From 50	€63.20 (75.21 € gross) *
From 100	€59.25 (70.51 € gross) *
From 250	€55.30 (65.81 € gross) *
From 500	€51.35 (61.11 € gross) *
From 1000	€47.40 (56.41 € gross) *

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Product information "FPGA Module with AMD Artix™ 7A15T-1C, 2 x 50 Pin-Header, 3,5 x 7,3 cm"

This product can no longer be ordered. A successor will be available in the store soon!
Further information is available on request.

The predecessor of this article is TE0725-02-15-1C. All changes are in the Product Change Notification (PCN).

The Trenz Electronic TE0725-03-15-1C is a low cost small-sized FPGA module integrating a AMD/Xilinx Artix™ 7 15T, 8 MByte HyperRAM and 32 MByte Flash memory for configuration and operation. The 2 x 50 pin header with a 2.54 mm standard pitch fits perfect on a perfboard.

This reference design is bundled with a FREE evaluation edition of the low-cost, commercially proven, high performance memory controller IP supplied by Synaptic Laboratories Ltd (SLL). This free IP evaluation license never expires, and no customer registration or NIC ID is required.
Click here to find the latest free trials of SLL’s memory controller IP for HyperBus, OctaBus, Xccela Bus, JEDEC xSPI Profile 1.0 and JEDEC xSPI Profile 2.0 for Intel, Microchip, and AMD/Xilinx FPGA. SLL IP is also qualified for use with Trenz Electronic HS CRUVI enabled boards. Please send all sales enquiry and technical support questions for SLL’s IP to info@synaptic-labs.com.

All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

AMD/Xilinx Artix™ 7 XC7A15T-1CSG324C
Commercial temperature grade (industrial on request)
3.5 x 7.3 cm form factor
32 MByte Flash memory
64 Mbit (8 MByte) HyperRAM
2 x 50 pin headers with 2.54 mm pitch, ideal for prefboard use
87 I/O's (42 + 42 + 3)
100 MHz system clock
I2C EEPROM
3.3 V single supply with on-board voltage regulators
JTAG/UART connector
2 LEDs
Optional POF Fiber Optical Adapter (125/250 MBit/s)

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado ML Standard Edition (free version)

The Vivado ML Standard Edition is the FREE version of the Vivado design suite. Vivado ML Standard delivers instant access to some basic Vivado features and functionality at no cost.

Overview of all editions of Vivado ML

Scope of Delivery

1 x TE0725-03-15-1C Trenz Electronic FPGA module with AMD/Xilinx Artix™ 7 15T
3 x pin header, straight, double row, for J1 and J2 as well as JB1

Additional Information

Manufacturer's article number: TE0725-03-15-1C
Trenz Electronic TE0725 Wiki
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Related links to "FPGA Module with AMD Artix™ 7A15T-1C, 2 x 50 Pin-Header, 3,5 x 7,3 cm"

Downloads

Digilent
OHO-Elektronik
SunDance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products

Online Documentation:

Trenz Electronic Wiki Documentation

Notes:

If you did not find the necessary documents, please send a request mail to Trenz Electronic Support (support[at]trenz-electronic.de).

-corporate - Certificates, Flyer, Catalog, ...
-obsolete_products
Accessories - Connectors, Heatsinks, ...
CPCIS_Cards - CompactPCI Serial Standard compatible boards with FPGA/SoC device
CRUVI
Development_Boards - complete Evaluation Platforms with FPGA/SoC device
Digital_IO - Levelconverter, like TE0101, TE0102, ...
FMC_Cards - compatible Adapterboards for FMC Connectors
JTAG_Programmer - for Xilinx, Intel and Lattice FPGA/SoC Devices
Modules_and_Module_Carriers - modules with FPGA/SoC device and corresponding carrier boards

Online Documentation:

Trenz Electronic Wiki Documentation » All SoMs and FPGA Modules

Notes:

If you did not find the necessary documents, please send a request mail to Trenz Electronic Support (support[at]trenz-electronic.de).

2.5x3.5 - form factor, like TE0717, ...
2.5x6.15 - form factor, like TEI0001, TEI0003, TEI0010, TEL0001, TEM0001, TEC0117, ...
2.5x7.07 - form factor, like TEI0050
2.5x8.65 - form factor, like TEI0015, TEI0016, ...
2.7x5.2 - form factor, like TE0890, ...
3.05x6.5 - form factor, like TE0876, ...
3.1x5.6 - form factor, like TEM0005 ...
3.5x7.3 - form factor, like TE0725, TE0725LP, ...

Online Documentation:

Trenz Electronic Wiki Documentation » All SoMs and FPGA Modules » 3.5 x 7.3 SoM Documentation

Notes:

If you did not find the necessary documents, please send a request mail to Trenz Electronic Support (support[at]trenz-electronic.de).

TE0725 - Xilinx Artix FPGA modules

Online Documentation:

Trenz Electronic Wiki Documentation » ... » TE0725 Resources

Notes:

If you did not find the necessary documents, please send a request mail to Trenz Electronic Support (support[at]trenz-electronic.de).

PCN - Product change notifications
REV02 - PCB Revision: Schematics, AD, STEP, HW Design Files and more ...
REV03 - PCB Revision: Schematics, AD, STEP, HW Design Files and more ...
Reference_Design - FPGA Design Examples for different Vivado Versions

Online Documentation:

Trenz Electronic Wiki Documentation » ... » TE0725 Reference Designs

Notes:

If you did not find the necessary documents, please send a request mail to Trenz Electronic Support (support[at]trenz-electronic.de).

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

2015.4
2016.1
2016.2
2017.4
2018.2
2019.2
2021.2
TE0725LP - Xilinx Artix FPGA modules
3x4 - form factor, like TE0714, ...
4.05x4.75 - form factor, like TE0763, ...
4.5x6.5 - form factor, like TE0716, ...
4x5 - form factor, like TE0820, TE0720, TE0715, TE0841, TE0741, TE0712, TE0711, ...
4x5.64 - form factor, like AM0010, ...
4x6 - form factor, like TE0724, ...
5.2x7.6 - form factor, like TE0808, TE0807, TE0803, TE0745, TE0729, ...
6.5x9 - form factor, like TE0835, ...
6x6 - form factor, like TE0728, ...
6x8 - form factor, like TEI0006, ...
7.5x10 - form factor, like TE0865, ...
8.5x8.5 - form factor, like TE0782, TE0783, TE0784 ...
USB_OEM_Modules - like TE0630, TE0320, TE0300, ...
special - form factor, like TE0726, TE0723, TE0722, TE0887, TEM0002 ...
Motherboards_and_Carriers - standalone carrier boards with FPGA/SoC device
PCIe_Cards - with FPGA/SoC Device on PCIe Card Format
Pinout - Pinout and Trace Length Viewer for Trenz Electronic PCBs
Pmods - compatible adapter for Pmod connectors
Shoparticle - Trenz Electronic Shop Article Selection Guide
Software - drivers, ToolZ, ...
third_party - Third party products containing Trenz PCBs
inrevium
reference

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

Key Features

Recommended Software

Scope of Delivery

Additional Information

TEC0850 Basic Design

CR00100 Basic Example

CR00100 Basic Example

CR00103 Certus Test

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0802 Basic Linux Example

TE0950 Basic Linux Example

TEI0022 Basic Example

TEI0022 Basic Example

TE0717 Hello World Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0001 Basic Example

TEI0003 LED Sequencer Example

TEI0003 NIOS SDRAM Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0003 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEI0010 Basic Example

TEM0001 Test Board Example

TEI0050 Basic Example

TEI0015 DAQ Capture Demo

TEI0015 Data Capture Demo

TEI0015 Jupyter Demo

TEI0016 DAQ Capture Demo

TEI0016 Data Capture Demo

TEI0016 Jupyter Demo

TEI0023 DAQ Capture Demo

TEI0023 Data Capture Demo

TEI0023 Jupyter Demo

TE0890 Hello World Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

Basic Linux Example

ZynqberryZero Demo VIDEO/AUDIO Design with RPI video camera stream to monitor

TEM0005 Webserver Demo1

MicroBlaze Basic-System

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725 HyperRAM Example

TE0725 Basic Example

TE0725LP Frequency Measurement

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0725LP Basic Example

TE0714 VIO LED Design

TE0714 Basic Barmetal Example

TE0763 Hello World Example

TE0710 MicroBlaze System

TE0710 UNIO MAC

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0710 Basic Linux Example

TE0711 F32C Demo Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0711 MicroBlaze Design

TE0712 MicroBlaze Basic-System

TE0712 Basic Linux Example

TE0712 Basic Linux Example

TE0712 Basic Linux Example