RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm

RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm

Price on request

expected to be available on 17-Jul-2025

Order number: TE0835-03-TXE81-A
In Stock: 0
Article status: Full production

The predecessor of this article is TE0835-02-TXE21-A. The Trenz Electronic TE0835 is... more

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Product information "RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm"

The predecessor of this article is TE0835-02-TXE21-A.

The Trenz Electronic TE0835 is an extended-grade module based on AMD Zynq™ UltraScale+™ RFSoC. The module is equipped with 4 x 1 GByte DDR4 SDRAM memory, 2 x 64 MByte SPI Flash memory, USB2.0, Ethernet transceiver and 2 x Samtec Razor Beam Board to Board (B2B) connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.

All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

SoC / FPGA
- Device: AMD Zynq™ UltraScale+™ RFSoC XCZU47DR-1FFVE1156E Gen3
- Other assembly options of this series are available with devices
  - ZU25, ZU27, ZU28 (Gen1)
  - ZU43, ZU48 (Gen3)
- Speedgrade: -1
- Temperature range: Extended
- Package: FFVE1156
- Engine: Quad-core Arm Cortex-A53 MPCore up to 1.3GHz
- 8 x 14-bit RF-ADCs with 5 GSPS
- 8 x 14-bit RF-DACs with 9.85 GSPS

RAM / Storage
- 4 x 1 GByte DDR4 SDRAM
- 2 x 64 MByte SPI Boot Flash (dual parallel)
- 2 Kbit I2C serial EEPROM with EUI-48 Node Identity

On Board
- Lattice MachXO2 CPLD
- Programmable ultra-high-performance DSPLL
- USB2.0 OTG transceiver
- Gigabit Ethernet transceiver
- 3 x Oscillators
- 4 x user LEDs

Interface
- 2 x Samtec Razor Beam ST5 (2 x 80 pol) Board to Board connectors
- Total I/O: 40 IOs, 20 LVDS, 32 MIO
- 8 x GTY
- 4 x GTR

Power
- 5V +/- 10 % Input Supply Voltage

Dimension
- 6,5 x 9 cm

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado ML Enterprise Edition

Development Support

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Scope of Delivery

1 x TE0835-03-TXE81-A Trenz Electronic RFSoC module with AMD Zynq™ UltraScale+™ RFSoC ZU47DR

Additional Information

Manufacturer's article number: TE0835-03-TXE81-A
Trenz Electronic TE0835 Wiki
AMD/Xilinx Zynq™ UltraScale+™ RFSoC Product Page
AMD/Xilinx Zynq™ UltraScale+™ RFSoC Product Selection Guide (PDF)
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Related links to "RFSoC Module with AMD Zynq™ UltraScale+™ ZU47DR-1E, 4 GByte DDR4, 6.5 x 9 cm"

Downloads

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

Directory		Content
PCN		Product change notifications: Important changes between hardware revisions
Reference Design		Reference Designs sort by ISE/EDK Version
REV0x		Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory		Content
PCN		Product change notifications: Important changes between hardware revisions
REV0x		Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

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