| Project Status (10/20/2010 - 11:03:51) | |||
| Project File: | system.xmp | Implementation State: | Programming File Generated |
| Module Name: | system |
|
No Errors |
| Product Version: | EDK 12.1 |
|
234 Warnings (87 new) |
| XPS Reports | [-] | ||||
| Report Name | Generated | Errors | Warnings | Infos | |
| Platgen Log File | tor 19. okt 21:50:56 2010 | 0 | 19 Warnings (0 new) | 105 Infos (1 new) | |
| Libgen Log File | sre 20. okt 10:32:32 2010 | 0 | 0 | 0 | |
| Simgen Log File | |||||
| BitInit Log File | sre 20. okt 10:33:19 2010 | 0 | 0 | 83 Infos (0 new) | |
| System Log File | sre 20. okt 11:03:51 2010 | ||||
| XPS Synthesis Summary | [-] | |||||
| Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors | |
| system | tor 19. okt 21:51:41 2010 | 8811 | 10734 | 30 | 0 | |
| mcb3_wrapper | tor 19. okt 21:50:46 2010 | 656 | 733 | 0 | ||
| mcb1_wrapper | tor 19. okt 21:50:20 2010 | 1707 | 2495 | 0 | ||
| spi_flash_wrapper | tor 19. okt 21:49:27 2010 | 242 | 240 | 0 | ||
| clock_generator_0_wrapper | tor 19. okt 21:49:18 2010 | 1 | 0 | |||
| xps_timer_0_wrapper | tor 19. okt 19:54:47 2010 | 361 | 334 | 0 | ||
| soft_temac_wrapper | tor 19. okt 19:54:39 2010 | 2722 | 3109 | 0 | ||
| soft_temac_wrapper_fifo_generator_v6_1_4_fifo_generator_v6_1_xst_1 | tor 19. okt 19:53:56 2010 | 126 | 174 | 0 | ||
| soft_temac_wrapper_blk_mem_gen_v4_1_blk_mem_gen_v4_1_xst_1 | tor 19. okt 19:52:55 2010 | 4 | 0 | |||
| soft_temac_wrapper_fifo_generator_v6_1_3_fifo_generator_v6_1_xst_1 | tor 19. okt 19:52:31 2010 | 71 | 36 | 1 | 0 | |
| soft_temac_wrapper_fifo_generator_v6_1_2_fifo_generator_v6_1_xst_1 | tor 19. okt 19:51:29 2010 | 71 | 116 | 4 | 0 | |
| soft_temac_wrapper_fifo_generator_v6_1_1_fifo_generator_v6_1_xst_1 | tor 19. okt 19:50:24 2010 | 41 | 67 | 1 | 0 | |
| plb_singlewire_0_wrapper | tor 19. okt 19:48:05 2010 | 285 | 429 | 0 | ||
| b2b_hdr1_wrapper | tor 19. okt 19:47:53 2010 | 126 | 65 | 0 | ||
| b2b_hdr2_wrapper | tor 19. okt 19:47:47 2010 | 98 | 53 | 0 | ||
| led_wrapper | tor 19. okt 19:47:40 2010 | 105 | 56 | 0 | ||
| rs232_wrapper | tor 19. okt 19:46:13 2010 | 145 | 132 | 0 | ||
| dlmb_wrapper | tor 19. okt 19:45:55 2010 | 1 | 1 | 0 | ||
| dlmb_cntlr_wrapper | tor 19. okt 19:45:52 2010 | 2 | 6 | 0 | ||
| ilmb_wrapper | tor 19. okt 19:45:50 2010 | 1 | 1 | 0 | ||
| ilmb_cntlr_wrapper | tor 19. okt 19:45:47 2010 | 2 | 6 | 0 | ||
| lmb_bram_wrapper | tor 19. okt 19:45:44 2010 | 16 | 0 | |||
| mb_plb_wrapper | tor 19. okt 19:45:39 2010 | 161 | 480 | 0 | ||
| mdm_0_wrapper | tor 19. okt 19:45:31 2010 | 119 | 120 | 0 | ||
| microblaze_0_wrapper | tor 19. okt 19:45:26 2010 | 1544 | 1890 | 4 | 0 | |
| proc_sys_reset_0_wrapper | tor 19. okt 19:44:56 2010 | 67 | 53 | 0 | ||
| xps_intc_0_wrapper | tor 19. okt 19:44:53 2010 | 158 | 137 | 0 | ||
| Device Utilization Summary | [-] | ||||
| Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Registers | 8,243 | 54,576 | 15% | ||
| Number used as Flip Flops | 8,238 | ||||
| Number used as Latches | 0 | ||||
| Number used as Latch-thrus | 4 | ||||
| Number used as AND/OR logics | 1 | ||||
| Number of Slice LUTs | 10,109 | 27,288 | 37% | ||
| Number used as logic | 8,328 | 27,288 | 30% | ||
| Number using O6 output only | 6,422 | ||||
| Number using O5 output only | 242 | ||||
| Number using O5 and O6 | 1,664 | ||||
| Number used as ROM | 0 | ||||
| Number used as Memory | 412 | 6,408 | 6% | ||
| Number used as Dual Port RAM | 254 | ||||
| Number using O6 output only | 10 | ||||
| Number using O5 output only | 18 | ||||
| Number using O5 and O6 | 226 | ||||
| Number used as Single Port RAM | 20 | ||||
| Number using O6 output only | 2 | ||||
| Number using O5 output only | 6 | ||||
| Number using O5 and O6 | 12 | ||||
| Number used as Shift Register | 138 | ||||
| Number using O6 output only | 63 | ||||
| Number using O5 output only | 1 | ||||
| Number using O5 and O6 | 74 | ||||
| Number used exclusively as route-thrus | 1,369 | ||||
| Number with same-slice register load | 1,343 | ||||
| Number with same-slice carry load | 22 | ||||
| Number with other load | 4 | ||||
| Number of occupied Slices | 3,682 | 6,822 | 53% | ||
| Number of LUT Flip Flop pairs used | 10,474 | ||||
| Number with an unused Flip Flop | 4,160 | 10,474 | 39% | ||
| Number with an unused LUT | 365 | 10,474 | 3% | ||
| Number of fully used LUT-FF pairs | 5,949 | 10,474 | 56% | ||
| Number of unique control sets | 605 | ||||
| Number of slice register sites lost to control set restrictions |
2,206 | 54,576 | 4% | ||
| Number of bonded IOBs | 137 | 316 | 43% | ||
| Number of LOCed IOBs | 137 | 137 | 100% | ||
| IOB Flip Flops | 38 | ||||
| Number of RAMB16BWERs | 29 | 116 | 25% | ||
| Number of RAMB8BWERs | 1 | 232 | 1% | ||
| Number of BUFIO2/BUFIO2_2CLKs | 3 | 32 | 9% | ||
| Number used as BUFIO2s | 3 | ||||
| Number used as BUFIO2_2CLKs | 0 | ||||
| Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
| Number of BUFG/BUFGMUXs | 6 | 16 | 37% | ||
| Number used as BUFGs | 5 | ||||
| Number used as BUFGMUX | 1 | ||||
| Number of DCM/DCM_CLKGENs | 0 | 8 | 0% | ||
| Number of ILOGIC2/ISERDES2s | 13 | 376 | 3% | ||
| Number used as ILOGIC2s | 13 | ||||
| Number used as ISERDES2s | 0 | ||||
| Number of IODELAY2/IODRP2/IODRP2_MCBs | 58 | 376 | 15% | ||
| Number used as IODELAY2s | 10 | ||||
| Number used as IODRP2s | 4 | ||||
| Number used as IODRP2_MCBs | 44 | ||||
| Number of OLOGIC2/OSERDES2s | 114 | 376 | 30% | ||
| Number used as OLOGIC2s | 22 | ||||
| Number used as OSERDES2s | 92 | ||||
| Number of BSCANs | 1 | 4 | 25% | ||
| Number of BUFHs | 0 | 256 | 0% | ||
| Number of BUFPLLs | 0 | 8 | 0% | ||
| Number of BUFPLL_MCBs | 2 | 4 | 50% | ||
| Number of DSP48A1s | 3 | 58 | 5% | ||
| Number of ICAPs | 0 | 1 | 0% | ||
| Number of MCBs | 2 | 2 | 100% | ||
| Number of PCILOGICSEs | 0 | 2 | 0% | ||
| Number of PLL_ADVs | 2 | 4 | 50% | ||
| Number of PMVs | 0 | 1 | 0% | ||
| Number of STARTUPs | 0 | 1 | 0% | ||
| Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
| Average Fanout of Non-Clock Nets | 3.92 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Translation Report | Current | tor 19. okt 21:52:08 2010 | 0 | 148 Warnings (1 new) | 6 Infos (4 new) | |
| Map Report | Current | tor 19. okt 22:03:14 2010 | 0 | 28 Warnings (28 new) | 518 Infos (2 new) | |
| Place and Route Report | Current | tor 19. okt 22:05:07 2010 | 0 | 30 Warnings (30 new) | 3 Infos (3 new) | |
| Post-PAR Static Timing Report | Current | tor 19. okt 22:05:34 2010 | 0 | 0 | 3 Infos (3 new) | |
| Bitgen Report | Current | tor 19. okt 22:06:13 2010 | 0 | 28 Warnings (28 new) | 1 Info (1 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Log File | Current | tor 19. okt 22:06:15 2010 | |