plb_singlewire Project Status | |||
Project File: | plb_singlewire.xise | Parser Errors: | No Errors |
Module Name: | plb_singlewire | Implementation State: | Synthesized |
Target Device: | xc5vlx30-3ff324 |
|
No Errors |
Product Version: | ISE 12.1 |
|
224 Warnings (221 new) |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 171 | 19200 | 0% | |
Number of Slice LUTs | 326 | 19200 | 1% | |
Number of fully used LUT-FF pairs | 72 | 425 | 16% | |
Number of bonded IOBs | 236 | 220 | 107% | |
Number of BUFG/BUFGCTRLs | 3 | 32 | 9% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | sre 30. jun 17:43:58 2010 | 0 | 224 Warnings (221 new) | 6 Infos (5 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |