Project Status (10/20/2010 - 11:03:51)
Project File: system.xmp Implementation State: Programming File Generated
Module Name: system
  • Errors:
No Errors
Product Version:EDK 12.1
  • Warnings:
234 Warnings (87 new)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log Filetor 19. okt 21:50:56 2010019 Warnings (0 new)105 Infos (1 new)
Libgen Log Filesre 20. okt 10:32:32 2010000
Simgen Log File    
BitInit Log Filesre 20. okt 10:33:19 20100083 Infos (0 new)
System Log Filesre 20. okt 11:03:51 2010   
 
XPS Synthesis Summary [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
systemtor 19. okt 21:51:41 2010881110734300
mcb3_wrappertor 19. okt 21:50:46 2010656733 0
mcb1_wrappertor 19. okt 21:50:20 201017072495 0
spi_flash_wrappertor 19. okt 21:49:27 2010242240 0
clock_generator_0_wrappertor 19. okt 21:49:18 2010 1 0
xps_timer_0_wrappertor 19. okt 19:54:47 2010361334 0
soft_temac_wrappertor 19. okt 19:54:39 201027223109 0
soft_temac_wrapper_fifo_generator_v6_1_4_fifo_generator_v6_1_xst_1tor 19. okt 19:53:56 2010126174 0
soft_temac_wrapper_blk_mem_gen_v4_1_blk_mem_gen_v4_1_xst_1tor 19. okt 19:52:55 2010  40
soft_temac_wrapper_fifo_generator_v6_1_3_fifo_generator_v6_1_xst_1tor 19. okt 19:52:31 2010713610
soft_temac_wrapper_fifo_generator_v6_1_2_fifo_generator_v6_1_xst_1tor 19. okt 19:51:29 20107111640
soft_temac_wrapper_fifo_generator_v6_1_1_fifo_generator_v6_1_xst_1tor 19. okt 19:50:24 2010416710
plb_singlewire_0_wrappertor 19. okt 19:48:05 2010285429 0
b2b_hdr1_wrappertor 19. okt 19:47:53 201012665 0
b2b_hdr2_wrappertor 19. okt 19:47:47 20109853 0
led_wrappertor 19. okt 19:47:40 201010556 0
rs232_wrappertor 19. okt 19:46:13 2010145132 0
dlmb_wrappertor 19. okt 19:45:55 201011 0
dlmb_cntlr_wrappertor 19. okt 19:45:52 201026 0
ilmb_wrappertor 19. okt 19:45:50 201011 0
ilmb_cntlr_wrappertor 19. okt 19:45:47 201026 0
lmb_bram_wrappertor 19. okt 19:45:44 2010  160
mb_plb_wrappertor 19. okt 19:45:39 2010161480 0
mdm_0_wrappertor 19. okt 19:45:31 2010119120 0
microblaze_0_wrappertor 19. okt 19:45:26 20101544189040
proc_sys_reset_0_wrappertor 19. okt 19:44:56 20106753 0
xps_intc_0_wrappertor 19. okt 19:44:53 2010158137 0
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 8,243 54,576 15%  
    Number used as Flip Flops 8,238      
    Number used as Latches 0      
    Number used as Latch-thrus 4      
    Number used as AND/OR logics 1      
Number of Slice LUTs 10,109 27,288 37%  
    Number used as logic 8,328 27,288 30%  
        Number using O6 output only 6,422      
        Number using O5 output only 242      
        Number using O5 and O6 1,664      
        Number used as ROM 0      
    Number used as Memory 412 6,408 6%  
        Number used as Dual Port RAM 254      
            Number using O6 output only 10      
            Number using O5 output only 18      
            Number using O5 and O6 226      
        Number used as Single Port RAM 20      
            Number using O6 output only 2      
            Number using O5 output only 6      
            Number using O5 and O6 12      
        Number used as Shift Register 138      
            Number using O6 output only 63      
            Number using O5 output only 1      
            Number using O5 and O6 74      
    Number used exclusively as route-thrus 1,369      
        Number with same-slice register load 1,343      
        Number with same-slice carry load 22      
        Number with other load 4      
Number of occupied Slices 3,682 6,822 53%  
Number of LUT Flip Flop pairs used 10,474      
    Number with an unused Flip Flop 4,160 10,474 39%  
    Number with an unused LUT 365 10,474 3%  
    Number of fully used LUT-FF pairs 5,949 10,474 56%  
    Number of unique control sets 605      
    Number of slice register sites lost
        to control set restrictions
2,206 54,576 4%  
Number of bonded IOBs 137 316 43%  
    Number of LOCed IOBs 137 137 100%  
    IOB Flip Flops 38      
Number of RAMB16BWERs 29 116 25%  
Number of RAMB8BWERs 1 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 3 32 9%  
    Number used as BUFIO2s 3      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 6 16 37%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 13 376 3%  
    Number used as ILOGIC2s 13      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 58 376 15%  
    Number used as IODELAY2s 10      
    Number used as IODRP2s 4      
    Number used as IODRP2_MCBs 44      
Number of OLOGIC2/OSERDES2s 114 376 30%  
    Number used as OLOGIC2s 22      
    Number used as OSERDES2s 92      
Number of BSCANs 1 4 25%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 2 4 50%  
Number of DSP48A1s 3 58 5%  
Number of ICAPs 0 1 0%  
Number of MCBs 2 2 100%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 2 4 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.92      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Translation ReportCurrenttor 19. okt 21:52:08 20100148 Warnings (1 new)6 Infos (4 new)
Map ReportCurrenttor 19. okt 22:03:14 2010028 Warnings (28 new)518 Infos (2 new)
Place and Route ReportCurrenttor 19. okt 22:05:07 2010030 Warnings (30 new)3 Infos (3 new)
Post-PAR Static Timing ReportCurrenttor 19. okt 22:05:34 2010003 Infos (3 new)
Bitgen ReportCurrenttor 19. okt 22:06:13 2010028 Warnings (28 new)1 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrenttor 19. okt 22:06:15 2010

Date Generated: 10/20/2010 - 11:03:51