System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
LMC_HOME C:\Xilinx\10\ISE\smartmodel\nt\installed_nt < data not available > < data not available > < data not available >
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
< data not available > < data not available > < data not available >
Path C:\Xilinx\12\ISE_DS\ISE\lib\nt;
C:\Xilinx\12\ISE_DS\ISE\bin\nt;
C:\Xilinx\12\ISE_DS\PlanAhead\bin;
C:\Xilinx\12\ISE_DS\EDK\bin\nt;
C:\Xilinx\12\ISE_DS\EDK\lib\nt;
C:\Xilinx\12\ISE_DS\common\bin\nt;
C:\Xilinx\12\ISE_DS\common\lib\nt;
C:\Xilinx\12\ChipScope\bin\nt;
C:\Xilinx\12\common\bin\nt;
C:\Xilinx\12\common\lib\nt;
C:\Xilinx\12\EDK\bin\nt;
C:\Xilinx\12\EDK\lib\nt;
C:\Xilinx\12\PlanAhead\bin;
C:\Xilinx\12\ISE\bin\nt;
C:\Xilinx\12\ISE\lib\nt;
C:\Xilinx\10\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;
C:\windows\system32;
C:\windows;
C:\windows\System32\Wbem;
C:\windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\WIDCOMM\Bluetooth Software\;
C:\Program Files\Altium Designer Winter 09\System;
C:\Program Files\Microsoft SQL Server\90\Tools\binn\;
C:\Program Files\MATLAB\R2008b\bin;
C:\Program Files\MATLAB\R2008b\bin\win32;
C:\Program Files\Intel\WiFi\bin\;
C:\Program Files\Common Files\Intel\WirelessCommon\;
C:\Xilinx\11\ModelSim\win32xoem
< data not available > < data not available > < data not available >
XILINX C:\Xilinx\12\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_DSP C:\Xilinx\12\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK C:\Xilinx\12\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD C:\Xilinx\12\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
XILINX_ROOT C:\Xilinx\12 < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   plb_singlewire.prj  
-ifmt   mixed MIXED
-ofn   plb_singlewire  
-ofmt   NGC NGC
-p   xc5vlx30-3-ff324  
-top   plb_singlewire  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-power Power Reduction NO NO
-iuc Use synthesis Constraints File NO NO
-lso Library Search Order plb_singlewire.lso  
-keep_hierarchy Keep Hierarchy NO NO
-netlist_hierarchy Netlist Hierarchy as_optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-dsp_utilization_ratio DSP Utilization Ratio 100 100%
-reduce_control_sets   off OFF
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   lut LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-use_dsp48   auto AUTO
-iobuf   YES YES
-max_fanout   100000 100000
-bufg   32 32
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Auto AUTO
-use_sync_set   Auto AUTO
-use_sync_reset   Auto AUTO
-iob   auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i7 CPU M 620 @ 2.67GHz/2660 MHz <  data not available  > <  data not available  > <  data not available  >
Host ales <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft <  data not available  > <  data not available  > <  data not available  >
OS Release major release (build 7600) <  data not available  > <  data not available  > <  data not available  >