MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ------------------------------------------------------- 1.00a jz 05/18/10 First release 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c, updated tcl file, added xaxidma_porting_guide.h 3.00a jz 11/22/10 Support IP core parameters change
Buffer Descriptor Alignment | |
#define | XAXIDMA_BD_MINIMUM_ALIGNMENT |
Maximum transfer length | |
This is determined by hardware | |
#define | XAXIDMA_MAX_TRANSFER_LEN |
Device registers | |
Register sets on TX and RX channels are identical | |
#define | XAXIDMA_TX_OFFSET |
#define | XAXIDMA_RX_OFFSET |
#define | XAXIDMA_CR_OFFSET |
#define | XAXIDMA_SR_OFFSET |
#define | XAXIDMA_CDESC_OFFSET |
#define | XAXIDMA_TDESC_OFFSET |
Bitmasks of XAXIDMA_CR_OFFSET register | |
#define | XAXIDMA_CR_RUNSTOP_MASK |
#define | XAXIDMA_CR_RESET_MASK |
Bitmasks of XAXIDMA_SR_OFFSET register | |
This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the _IRQ_ section.
The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section. | |
#define | XAXIDMA_HALTED_MASK |
#define | XAXIDMA_IDLE_MASK |
#define | XAXIDMA_ERR_INTERNAL_MASK |
#define | XAXIDMA_ERR_SLAVE_MASK |
#define | XAXIDMA_ERR_DECODE_MASK |
#define | XAXIDMA_ERR_SG_INT_MASK |
#define | XAXIDMA_ERR_SG_SLV_MASK |
#define | XAXIDMA_ERR_SG_DEC_MASK |
#define | XAXIDMA_ERR_ALL_MASK |
Bitmask for interrupts | |
These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register | |
#define | XAXIDMA_IRQ_IOC_MASK |
#define | XAXIDMA_IRQ_DELAY_MASK |
#define | XAXIDMA_IRQ_ERROR_MASK |
#define | XAXIDMA_IRQ_ALL_MASK |
Bitmask and shift for delay and coalesce | |
These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register | |
#define | XAXIDMA_DELAY_MASK |
#define | XAXIDMA_COALESCE_MASK |
#define | XAXIDMA_DELAY_SHIFT |
#define | XAXIDMA_COALESCE_SHIFT |
Buffer Descriptor offsets | |
USR* fields are defined by higher level IP. setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only. | |
#define | XAXIDMA_BD_NDESC_OFFSET |
#define | XAXIDMA_BD_BUFA_OFFSET |
#define | XAXIDMA_BD_CTRL_LEN_OFFSET |
#define | XAXIDMA_BD_STS_OFFSET |
#define | XAXIDMA_BD_USR0_OFFSET |
#define | XAXIDMA_BD_USR1_OFFSET |
#define | XAXIDMA_BD_USR2_OFFSET |
#define | XAXIDMA_BD_USR3_OFFSET |
#define | XAXIDMA_BD_USR4_OFFSET |
#define | XAXIDMA_BD_ID_OFFSET |
#define | XAXIDMA_BD_HAS_STSCNTRL_OFFSET |
#define | XAXIDMA_BD_HAS_DRE_OFFSET |
#define | XAXIDMA_BD_HAS_DRE_MASK |
#define | XAXIDMA_BD_WORDLEN_MASK |
#define | XAXIDMA_BD_HAS_DRE_SHIFT |
#define | XAXIDMA_BD_WORDLEN_SHIFT |
#define | XAXIDMA_BD_START_CLEAR |
#define | XAXIDMA_BD_BYTES_TO_CLEAR |
#define | XAXIDMA_BD_NUM_WORDS |
#define | XAXIDMA_BD_HW_NUM_BYTES |
#define | XAXIDMA_LAST_APPWORD |
Bitmasks of XAXIDMA_BD_CTRL_OFFSET register | |
#define | XAXIDMA_BD_CTRL_LENGTH_MASK |
#define | XAXIDMA_BD_CTRL_TXSOF_MASK |
#define | XAXIDMA_BD_CTRL_TXEOF_MASK |
#define | XAXIDMA_BD_CTRL_ALL_MASK |
Bitmasks of XAXIDMA_BD_STS_OFFSET register | |
#define | XAXIDMA_BD_STS_ACTUAL_LEN_MASK |
#define | XAXIDMA_BD_STS_COMPLETE_MASK |
#define | XAXIDMA_BD_STS_DEC_ERR_MASK |
#define | XAXIDMA_BD_STS_SLV_ERR_MASK |
#define | XAXIDMA_BD_STS_INT_ERR_MASK |
#define | XAXIDMA_BD_STS_ALL_ERR_MASK |
#define | XAXIDMA_BD_STS_RXSOF_MASK |
#define | XAXIDMA_BD_STS_RXEOF_MASK |
#define | XAXIDMA_BD_STS_ALL_MASK |
Defines | |
#define | XAxiDma_ReadReg(BaseAddress, RegOffset) |
#define | XAxiDma_WriteReg(BaseAddress, RegOffset, Data) |
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Buffer address |
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BD specific bytes to be cleared |
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All control bits |
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Control/buffer length |
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Requested len |
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Last tx packet |
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First tx packet |
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Whether has DRE mask |
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Whether has DRE |
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Whether has DRE shift |
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Whether has stscntrl strm |
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Number of bytes hw used |
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Sw ID |
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Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs |
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Next descriptor pointer |
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Total number of words for one BD |
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Offset to start clear |
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Actual len |
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All errors |
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All status bits |
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Completed |
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Decode error |
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Internal err |
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Status |
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Last rx pkt |
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First rx pkt |
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Slave error |
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User IP specific word0 |
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User IP specific word1 |
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User IP specific word2 |
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User IP specific word3 |
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User IP specific word4 |
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Whether has DRE mask |
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Whether has DRE shift |
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Current descriptor pointer |
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Coalesce counter |
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Channel control |
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Reset DMA engine |
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Start/stop DMA channel |
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Delay timeout counter |
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All errors |
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Datamover decode err |
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Datamover internal err |
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SG decode err |
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SG internal err |
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SG slave err |
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Datamover slave err |
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DMA channel halted |
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DMA channel idle |
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All interrupts |
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Delay interrupt |
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Error interrupt |
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Completion intr |
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Read the given register.
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RX channel registers base offset |
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Status |
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Tail descriptor pointer |
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TX channel registers base offset |
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Write the given register.
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