Name |
Value |
C_M3_AXIS_DATA_WIDTH |
32 |
C_S3_AXIS_DATA_WIDTH |
32 |
C_M4_AXIS_DATA_WIDTH |
32 |
C_S4_AXIS_DATA_WIDTH |
32 |
C_M5_AXIS_DATA_WIDTH |
32 |
C_S5_AXIS_DATA_WIDTH |
32 |
C_M6_AXIS_DATA_WIDTH |
32 |
C_S6_AXIS_DATA_WIDTH |
32 |
C_M7_AXIS_DATA_WIDTH |
32 |
C_S7_AXIS_DATA_WIDTH |
32 |
C_M8_AXIS_DATA_WIDTH |
32 |
C_S8_AXIS_DATA_WIDTH |
32 |
C_M9_AXIS_DATA_WIDTH |
32 |
C_S9_AXIS_DATA_WIDTH |
32 |
C_M10_AXIS_DATA_WIDTH |
32 |
C_S10_AXIS_DATA_WIDTH |
32 |
C_M11_AXIS_DATA_WIDTH |
32 |
C_S11_AXIS_DATA_WIDTH |
32 |
C_M12_AXIS_DATA_WIDTH |
32 |
C_S12_AXIS_DATA_WIDTH |
32 |
C_M13_AXIS_DATA_WIDTH |
32 |
C_S13_AXIS_DATA_WIDTH |
32 |
C_M14_AXIS_DATA_WIDTH |
32 |
C_S14_AXIS_DATA_WIDTH |
32 |
C_M15_AXIS_DATA_WIDTH |
32 |
C_S15_AXIS_DATA_WIDTH |
32 |
C_ICACHE_BASEADDR |
0xC0000000 |
C_ICACHE_HIGHADDR |
0xC7FFFFFF |
C_USE_ICACHE |
1 |
C_ALLOW_ICACHE_WR |
1 |
C_ADDR_TAG_BITS |
17 |
C_CACHE_BYTE_SIZE |
8192 |
C_ICACHE_USE_FSL |
1 |
C_ICACHE_LINE_LEN |
8 |
C_ICACHE_ALWAYS_USED |
1 |
C_ICACHE_INTERFACE |
0 |
C_ICACHE_VICTIMS |
8 |
C_ICACHE_STREAMS |
1 |
C_ICACHE_FORCE_TAG_LUTRAM |
0 |
C_ICACHE_DATA_WIDTH |
0 |
C_M_AXI_IC_SUPPORTS_THREADS |
0 |
C_M_AXI_IC_THREAD_ID_WIDTH |
1 |
C_M_AXI_IC_SUPPORTS_READ |
1 |
C_M_AXI_IC_SUPPORTS_WRITE |
0 |
C_M_AXI_IC_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_IC_DATA_WIDTH |
32 |
C_M_AXI_IC_ADDR_WIDTH |
32 |
C_M_AXI_IC_PROTOCOL |
AXI4 |
C_M_AXI_IC_USER_VALUE |
0b11111 |
C_M_AXI_IC_SUPPORTS_USER_SIGNALS |
1 |
C_M_AXI_IC_AWUSER_WIDTH |
5 |
C_M_AXI_IC_ARUSER_WIDTH |
5 |
C_M_AXI_IC_WUSER_WIDTH |
1 |
C_M_AXI_IC_RUSER_WIDTH |
1 |
C_M_AXI_IC_BUSER_WIDTH |
1 |
C_INTERCONNECT_M_AXI_IC_READ_ISSUING |
2 |
C_DCACHE_BASEADDR |
0xC0000000 |
C_DCACHE_HIGHADDR |
0xC7FFFFFF |
C_USE_DCACHE |
1 |
C_ALLOW_DCACHE_WR |
1 |
C_DCACHE_ADDR_TAG |
17 |
C_DCACHE_BYTE_SIZE |
8192 |
C_DCACHE_USE_FSL |
1 |
C_DCACHE_LINE_LEN |
8 |
C_DCACHE_ALWAYS_USED |
1 |
C_DCACHE_INTERFACE |
0 |
C_DCACHE_USE_WRITEBACK |
1 |
C_DCACHE_VICTIMS |
8 |
C_DCACHE_FORCE_TAG_LUTRAM |
0 |
C_DCACHE_DATA_WIDTH |
0 |
C_M_AXI_DC_SUPPORTS_THREADS |
0 |
C_M_AXI_DC_THREAD_ID_WIDTH |
1 |
C_M_AXI_DC_SUPPORTS_READ |
1 |
C_M_AXI_DC_SUPPORTS_WRITE |
1 |
C_M_AXI_DC_SUPPORTS_NARROW_BURST |
0 |
C_M_AXI_DC_DATA_WIDTH |
32 |
C_M_AXI_DC_ADDR_WIDTH |
32 |
C_M_AXI_DC_PROTOCOL |
AXI4 |
C_M_AXI_DC_EXCLUSIVE_ACCESS |
0 |
C_M_AXI_DC_USER_VALUE |
0b11111 |
C_M_AXI_DC_SUPPORTS_USER_SIGNALS |
1 |
C_M_AXI_DC_AWUSER_WIDTH |
5 |
C_M_AXI_DC_ARUSER_WIDTH |
5 |
C_M_AXI_DC_WUSER_WIDTH |
1 |
C_M_AXI_DC_RUSER_WIDTH |
1 |
C_M_AXI_DC_BUSER_WIDTH |
1 |
C_INTERCONNECT_M_AXI_DC_READ_ISSUING |
2 |
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING |
32 |
C_USE_MMU |
0 |
C_MMU_DTLB_SIZE |
4 |
C_MMU_ITLB_SIZE |
2 |
C_MMU_TLB_ACCESS |
3 |
C_MMU_ZONES |
16 |
C_MMU_PRIVILEGED_INSTR |
0 |
C_USE_INTERRUPT |
0 |
C_USE_EXT_BRK |
0 |
C_USE_EXT_NM_BRK |
0 |
C_USE_BRANCH_TARGET_CACHE |
1 |
C_BRANCH_TARGET_CACHE_SIZE |
0 |
C_INTERCONNECT_M_AXI_DC_AW_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DC_W_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DP_AW_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DP_AR_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DP_W_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DP_R_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DP_B_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DC_AR_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DC_R_REGISTER |
1 |
C_INTERCONNECT_M_AXI_DC_B_REGISTER |
1 |
C_INTERCONNECT_M_AXI_IC_AW_REGISTER |
1 |
C_INTERCONNECT_M_AXI_IC_AR_REGISTER |
1 |
C_INTERCONNECT_M_AXI_IC_W_REGISTER |
1 |
C_INTERCONNECT_M_AXI_IC_R_REGISTER |
1 |
C_INTERCONNECT_M_AXI_IC_B_REGISTER |
1 |
|