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xaxidma_hw.h File Reference


Detailed Description

Hardware definition file. It defines the register interface and Buffer Descriptor (BD) definitions.

 MODIFICATION HISTORY:

 Ver   Who  Date     Changes
 ----- ---- -------- -------------------------------------------------------
 1.00a jz   05/18/10 First release
 2.00a jz   08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
                     updated tcl file, added xaxidma_porting_guide.h
 3.00a jz   11/22/10 Support IP core parameters change
 


Buffer Descriptor Alignment

#define XAXIDMA_BD_MINIMUM_ALIGNMENT

Maximum transfer length

This is determined by hardware

#define XAXIDMA_MAX_TRANSFER_LEN

Device registers

Register sets on TX and RX channels are identical

#define XAXIDMA_TX_OFFSET
#define XAXIDMA_RX_OFFSET
#define XAXIDMA_CR_OFFSET
#define XAXIDMA_SR_OFFSET
#define XAXIDMA_CDESC_OFFSET
#define XAXIDMA_TDESC_OFFSET

Bitmasks of XAXIDMA_CR_OFFSET register

#define XAXIDMA_CR_RUNSTOP_MASK
#define XAXIDMA_CR_RESET_MASK

Bitmasks of XAXIDMA_SR_OFFSET register

This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts (note that interrupt masks are shared with XAXIDMA_CR_OFFSET register, and are defined in the _IRQ_ section.

The interrupt coalescing threshold value and delay counter value are also shared with XAXIDMA_CR_OFFSET register, and are defined in a later section.

#define XAXIDMA_HALTED_MASK
#define XAXIDMA_IDLE_MASK
#define XAXIDMA_ERR_INTERNAL_MASK
#define XAXIDMA_ERR_SLAVE_MASK
#define XAXIDMA_ERR_DECODE_MASK
#define XAXIDMA_ERR_SG_INT_MASK
#define XAXIDMA_ERR_SG_SLV_MASK
#define XAXIDMA_ERR_SG_DEC_MASK
#define XAXIDMA_ERR_ALL_MASK

Bitmask for interrupts

These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register

#define XAXIDMA_IRQ_IOC_MASK
#define XAXIDMA_IRQ_DELAY_MASK
#define XAXIDMA_IRQ_ERROR_MASK
#define XAXIDMA_IRQ_ALL_MASK

Bitmask and shift for delay and coalesce

These masks are shared by XAXIDMA_CR_OFFSET register and XAXIDMA_SR_OFFSET register

#define XAXIDMA_DELAY_MASK
#define XAXIDMA_COALESCE_MASK
#define XAXIDMA_DELAY_SHIFT
#define XAXIDMA_COALESCE_SHIFT

Buffer Descriptor offsets

USR* fields are defined by higher level IP. setup for EMAC type devices. The first 13 words are used by hardware. All words after the 13rd word are for software use only.

#define XAXIDMA_BD_NDESC_OFFSET
#define XAXIDMA_BD_BUFA_OFFSET
#define XAXIDMA_BD_CTRL_LEN_OFFSET
#define XAXIDMA_BD_STS_OFFSET
#define XAXIDMA_BD_USR0_OFFSET
#define XAXIDMA_BD_USR1_OFFSET
#define XAXIDMA_BD_USR2_OFFSET
#define XAXIDMA_BD_USR3_OFFSET
#define XAXIDMA_BD_USR4_OFFSET
#define XAXIDMA_BD_ID_OFFSET
#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET
#define XAXIDMA_BD_HAS_DRE_OFFSET
#define XAXIDMA_BD_HAS_DRE_MASK
#define XAXIDMA_BD_WORDLEN_MASK
#define XAXIDMA_BD_HAS_DRE_SHIFT
#define XAXIDMA_BD_WORDLEN_SHIFT
#define XAXIDMA_BD_START_CLEAR
#define XAXIDMA_BD_BYTES_TO_CLEAR
#define XAXIDMA_BD_NUM_WORDS
#define XAXIDMA_BD_HW_NUM_BYTES
#define XAXIDMA_LAST_APPWORD

Bitmasks of XAXIDMA_BD_CTRL_OFFSET register

#define XAXIDMA_BD_CTRL_LENGTH_MASK
#define XAXIDMA_BD_CTRL_TXSOF_MASK
#define XAXIDMA_BD_CTRL_TXEOF_MASK
#define XAXIDMA_BD_CTRL_ALL_MASK

Bitmasks of XAXIDMA_BD_STS_OFFSET register

#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK
#define XAXIDMA_BD_STS_COMPLETE_MASK
#define XAXIDMA_BD_STS_DEC_ERR_MASK
#define XAXIDMA_BD_STS_SLV_ERR_MASK
#define XAXIDMA_BD_STS_INT_ERR_MASK
#define XAXIDMA_BD_STS_ALL_ERR_MASK
#define XAXIDMA_BD_STS_RXSOF_MASK
#define XAXIDMA_BD_STS_RXEOF_MASK
#define XAXIDMA_BD_STS_ALL_MASK

Defines

#define XAxiDma_ReadReg(BaseAddress, RegOffset)
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data)


Define Documentation

#define XAXIDMA_BD_BUFA_OFFSET
 

Buffer address

#define XAXIDMA_BD_BYTES_TO_CLEAR
 

BD specific bytes to be cleared

#define XAXIDMA_BD_CTRL_ALL_MASK
 

All control bits

#define XAXIDMA_BD_CTRL_LEN_OFFSET
 

Control/buffer length

#define XAXIDMA_BD_CTRL_LENGTH_MASK
 

Requested len

#define XAXIDMA_BD_CTRL_TXEOF_MASK
 

Last tx packet

#define XAXIDMA_BD_CTRL_TXSOF_MASK
 

First tx packet

#define XAXIDMA_BD_HAS_DRE_MASK
 

Whether has DRE mask

#define XAXIDMA_BD_HAS_DRE_OFFSET
 

Whether has DRE

#define XAXIDMA_BD_HAS_DRE_SHIFT
 

Whether has DRE shift

#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET
 

Whether has stscntrl strm

#define XAXIDMA_BD_HW_NUM_BYTES
 

Number of bytes hw used

#define XAXIDMA_BD_ID_OFFSET
 

Sw ID

#define XAXIDMA_BD_MINIMUM_ALIGNMENT
 

Minimum byte alignment requirement for descriptors to satisfy both hardware/software needs

#define XAXIDMA_BD_NDESC_OFFSET
 

Next descriptor pointer

#define XAXIDMA_BD_NUM_WORDS
 

Total number of words for one BD

#define XAXIDMA_BD_START_CLEAR
 

Offset to start clear

#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK
 

Actual len

#define XAXIDMA_BD_STS_ALL_ERR_MASK
 

All errors

#define XAXIDMA_BD_STS_ALL_MASK
 

All status bits

#define XAXIDMA_BD_STS_COMPLETE_MASK
 

Completed

#define XAXIDMA_BD_STS_DEC_ERR_MASK
 

Decode error

#define XAXIDMA_BD_STS_INT_ERR_MASK
 

Internal err

#define XAXIDMA_BD_STS_OFFSET
 

Status

#define XAXIDMA_BD_STS_RXEOF_MASK
 

Last rx pkt

#define XAXIDMA_BD_STS_RXSOF_MASK
 

First rx pkt

#define XAXIDMA_BD_STS_SLV_ERR_MASK
 

Slave error

#define XAXIDMA_BD_USR0_OFFSET
 

User IP specific word0

#define XAXIDMA_BD_USR1_OFFSET
 

User IP specific word1

#define XAXIDMA_BD_USR2_OFFSET
 

User IP specific word2

#define XAXIDMA_BD_USR3_OFFSET
 

User IP specific word3

#define XAXIDMA_BD_USR4_OFFSET
 

User IP specific word4

#define XAXIDMA_BD_WORDLEN_MASK
 

Whether has DRE mask

#define XAXIDMA_BD_WORDLEN_SHIFT
 

Whether has DRE shift

#define XAXIDMA_CDESC_OFFSET
 

Current descriptor pointer

#define XAXIDMA_COALESCE_MASK
 

Coalesce counter

#define XAXIDMA_CR_OFFSET
 

Channel control

#define XAXIDMA_CR_RESET_MASK
 

Reset DMA engine

#define XAXIDMA_CR_RUNSTOP_MASK
 

Start/stop DMA channel

#define XAXIDMA_DELAY_MASK
 

Delay timeout counter

#define XAXIDMA_ERR_ALL_MASK
 

All errors

#define XAXIDMA_ERR_DECODE_MASK
 

Datamover decode err

#define XAXIDMA_ERR_INTERNAL_MASK
 

Datamover internal err

#define XAXIDMA_ERR_SG_DEC_MASK
 

SG decode err

#define XAXIDMA_ERR_SG_INT_MASK
 

SG internal err

#define XAXIDMA_ERR_SG_SLV_MASK
 

SG slave err

#define XAXIDMA_ERR_SLAVE_MASK
 

Datamover slave err

#define XAXIDMA_HALTED_MASK
 

DMA channel halted

#define XAXIDMA_IDLE_MASK
 

DMA channel idle

#define XAXIDMA_IRQ_ALL_MASK
 

All interrupts

#define XAXIDMA_IRQ_DELAY_MASK
 

Delay interrupt

#define XAXIDMA_IRQ_ERROR_MASK
 

Error interrupt

#define XAXIDMA_IRQ_IOC_MASK
 

Completion intr

#define XAxiDma_ReadReg BaseAddress,
RegOffset   ) 
 

Read the given register.

Parameters:
BaseAddress is the base address of the device
RegOffset is the register offset to be read
Returns:
The 32-bit value of the register
Note:
C-style signature: u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)

#define XAXIDMA_RX_OFFSET
 

RX channel registers base offset

#define XAXIDMA_SR_OFFSET
 

Status

#define XAXIDMA_TDESC_OFFSET
 

Tail descriptor pointer

#define XAXIDMA_TX_OFFSET
 

TX channel registers base offset

#define XAxiDma_WriteReg BaseAddress,
RegOffset,
Data   ) 
 

Write the given register.

Parameters:
BaseAddress is the base address of the device
RegOffset is the register offset to be written
Data is the 32-bit value to write to the register
Returns:
None.
Note:
C-style signature: void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)