---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:59:23 12/17/2013 -- Design Name: -- Module Name: top - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity blinky is Port ( LED1 : out STD_LOGIC; LED2 : out STD_LOGIC ); end blinky; architecture Behavioral of blinky is signal icnt: std_logic_vector(31 downto 0); signal iclk: std_logic; begin LED1 <= icnt(26); LED2 <= icnt(25); process(iclk) begin if (rising_edge(iclk)) then icnt <= icnt + X"00000001"; end if; end process; STARTUPE2_inst : STARTUPE2 generic map ( PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams. SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation. ) port map ( CFGCLK => open, -- 1-bit output: Configuration main clock output CFGMCLK => iclk, -- 1-bit output: Configuration internal oscillator clock output EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup. PREQ => open, -- 1-bit output: PROGRAM request to fabric output CLK => '0', -- 1-bit input: User start-up clock input GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name) KEYCLEARB => '0' , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) PACK => '1', -- 1-bit input: PROGRAM acknowledge input USRCCLKO => '1', -- 1-bit input: User CCLK input USRCCLKTS => '1', -- 1-bit input: User CCLK 3-state enable input USRDONEO => '1', -- 1-bit input: User DONE pin output control USRDONETS => '1' -- 1-bit input: User DONE 3-state enable output ); end Behavioral;