----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:59:23 12/17/2013 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity top is Port ( 
           CLK_MGT_P  : in  STD_LOGIC;
		   CLK_MGT_N  : in  STD_LOGIC;

           CLK_P  : in  STD_LOGIC;
		   CLK_N  : in  STD_LOGIC;
		   
		   
		   EN_CLK   : out  STD_LOGIC;
		   
	       LED1   : out  STD_LOGIC;
           LED2   : out  STD_LOGIC
		   );
end top;

architecture Behavioral of top is

signal cnt: std_logic_vector(31 downto 0);
signal mcnt: std_logic_vector(31 downto 0);

signal mgtclk: std_logic;
signal clk: std_logic;


   attribute CLKCM_CFG    : string ;
   attribute CLKRCV_TRST  : string ;
   attribute CLKSWING_CFG : string ;
   attribute BOX_TYPE     : string ;
   signal XLXI_1_CEB_openSignal : std_logic;
   signal XLXI_1_I_openSignal   : std_logic;
   signal XLXI_1_IB_openSignal  : std_logic;
   component IBUFDS_GTE2
      -- synopsys translate_off
      generic( CLKCM_CFG : boolean :=  TRUE;
               CLKRCV_TRST : boolean :=  TRUE;
               CLKSWING_CFG : boolean :=  TRUE);
      -- synopsys translate_on
      port ( CEB   : in    std_logic; 
             I     : in    std_logic; 
             IB    : in    std_logic; 
             O     : out   std_logic; 
             ODIV2 : out   std_logic);
   end component;
   attribute CLKCM_CFG of IBUFDS_GTE2 : component is "TRUE";
   attribute CLKRCV_TRST of IBUFDS_GTE2 : component is "TRUE";
   --attribute CLKSWING_CFG of IBUFDS_GTE2 : component is "TRUE";
   attribute BOX_TYPE of IBUFDS_GTE2 : component is "BLACK_BOX";
   
begin
    EN_CLK <= '1';
	
	LED1 <= cnt(26);
	LED2 <= mcnt(25);
  

	GTE_BUF_Inst : IBUFDS_GTE2
			port map (
				CEB=>'0',
                I=>CLK_MGT_P,
                IB=>CLK_MGT_N,
                O=>mgtclk,
                ODIV2=>open
			);

	CLK_BUF_Inst : IBUFDS
		port map (
			I	=> CLK_P,
			IB 	=> CLK_N,
			O 	=> clk
			);

	
	
process(clk)
begin
	if (rising_edge(clk)) then
			cnt <= cnt + X"00000001";
	end if;
end process;


process(mgtclk)
begin
	if (rising_edge(mgtclk)) then
			mcnt <= mcnt + X"00000001";
	end if;
end process;



end Behavioral;