| File | File-Extension | Description |
|---|---|---|
| Bit-File | *.bit | FPGA Configuration File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| IP-Interfaces | I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | I2C,SPI-Flash,UART |
| TE-IP | ASIO (AXI-Stream to IO) |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | VIO |
| TE-IP | Startupe2,LabTools Frequency Counter |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Component | Description |
|---|---|
| Xilinx-IP | VIO (Virtual Input/Output) |
| TE-IP | Labtools Frequency Counter, Startupe2 Primitive Wrapper |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Directory | Content | ||
|---|---|---|---|
| PCN | Product change notifications: Important changes between hardware revisions | ||
| Reference Design | Reference Designs sort by ISE/EDK Version | ||
| REV0x | Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs | ||
| Documents | PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and... | ||
| Firmware | Initial configuration for diverse PCB components, like CPLD, PLL and ... | ||
| HW Design | Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ... | ||
| Pictures | PCB-Pictures | ||
| Directory | Content | ||
|---|---|---|---|
| PCN | Product change notifications: Important changes between hardware revisions | ||
| REV0x | Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs | ||
| Documents | PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and... | ||
| Firmware | Initial configuration for diverse PCB components, like CPLD, PLL and ... | ||
| HW Design | Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ... | ||
| Pictures | PCB-Pictures | ||
| Component | Description |
|---|---|
| Interface IPs | DDR3, GPIO, Uart0, QSPI and Ethernet |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example (.elf file only) |
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite |
| TE-IP | ASIO GPIO (AXI-Stream to GPIO) |
| Application | Description |
|---|---|
| Hello World | Xilinx Hello world ( generate elf file only) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | VIO,ILA |
| TE-IP | unio_mac |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Component | Description |
|---|---|
| Interface IPs | QSPI, Uart, ASIO (Axi-Stream to IO) |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | ILA, VIO, CLK-Wizard |
| TE-IP | F32C, Vector_LED, UART_MON |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Component | Description |
|---|---|
| IP-Interfaces | DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO) |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example (.elf only) |
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO |
| TE-IP | ASIO (AXI-Stream to IO), labtools_fmeter |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example (.elf only) |
| te_spi_bootloader | SPI Bootloader (.elf only) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example (.elf only) |
| memory_tests | Xilinx Memory Example (.elf only) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/) |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image for Zynq-FPGAs |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlace Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,1x SD,1x Ethernet |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image for Zynq-FPGAs |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlace Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated: I2C0, I2C1, Uart0, Uart1, GPIO, SD0, USB0, ENET0, Q-SPI |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with Ethernet, USB |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, DDR, I2C0,I2C1, UART0, UART1, GPIO, SD0, USB0, ETH0, TTC |
| Xilinx-IP | VIO |
| TE-IP | Labtools_Fmeter |
| Application | Description |
|---|---|
| zynq_fsbl | Default Xilinx FSBL |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB,RTC, Init Script(run init.sh from SD on startup). |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,1x SD,1x Ethernet |
| TE-IP | TE0720 System-Controller |
| TE-IP | Video IO to HDMI |
| TE-IP | AXI-Stream FB Converter |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/) |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image for Zynq-FPGAs |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlace Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C, 2x SPI,2x SD, USB, Ethernet |
| TE-IP | TE0720 System-Controller |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C, 2x SPI,2x SD, USB, Ethernet |
| Xilinx-IP | VIO |
| TE-IP | TE0701 System Controller(SC0701), STARTUPE2 Primitive |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified) |
| hello_world | TE0720 Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| Source Name | <design_name><folder> | Source Description |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with Ethernet,USB,RTC |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated:SPI0, SPI1, I2C0, UAR0, UART1, GPIO, SD0, SD1, USB0, ENET0,ENET1, QSPI |
| Xilinx-IP | GMII to RGMII |
| TE-IP | TE0720 System-Controller |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with Ethernet,USB,RTC |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated:SPI0, SPI1, I2C0, UAR0, UART1, GPIO, SD0, SD1, USB0, ENET0, QSPI |
| TE-IP | TE0720 System-Controller |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with Ethernet,USB,RTC |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | SPI0, SPI1, QSPI, I2C0, I2C1, UART0, UART1, GPIO, SD0, SD1, USB0, ETH0, DDR3 |
| TE-IP | TE0720 System Controller IO |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL, see te_fsbl_hooks.c (template in subfolder sw_lib) |
| Hello TE0720 | Hello TE0720 in endless loop |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, DDR3, SPI0, SPI1, QSPI, I2C0, I2C1, UART0, UART1, GPIO, SD0, SD1, USB0, ETH0 |
| Xilinx-IP | VIO |
| TE-IP | TE0720 System Controller IO |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL, see te_fsbl_hooks.c (template in subfolder sw_lib) |
| Hello TE0720 | Hello TE0720 in endless loop |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB, RTC, Init Script(run init.sh from SD on startup). |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
JTAG to SPI bitfiles for XC3SPROG JTAG SPI Programming tool
| File | File-Extension | Description |
|---|---|---|
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Bit-File | *.bit | FPGA Configuration File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Xilinx-IP | ILA, VIO, CLK-Wizard |
| TE-IP | F32C, Vector_LED, UART_MON |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| Component | Description |
|---|---|
| Xilinx-IP | IBERT |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD0, SD1, I2C, UART0 |
| Xilinx-IP | VIO |
| TE-IP | LabTools FMeter |
| Application | Description |
|---|---|
| zynqmp_fsbl | Modified FSBL for Si5338 Configuration and ETH/USB Reset (template in sub-folder /sw_lib/sw_apps/zynqmp_fsbl) |
| hello_world | Xilinx Hello World example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| Si5338 | /misc/SI5338 | Si5338ClockBuilder Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB,ETH,I2C,SD |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, GEM3, USB0, SD0(eMMC), SD1(SD), I2C0, UART0, DDR4 |
| Xilinx-IP | VIO |
| TE-IP | LabTools FMeter |
| Application | Description |
|---|---|
| zynqmp_fsbl | TE modified Zynq FSBL for SI5338 Configuration (template in subfolder sw_lib) |
| zynqmp_pmufw | Xilinx default PMU |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Xilinx-IP | MicroBlaze, MB-Debug, Uartlite, 2x DDR4 SDRAM MIG, I2C, QSPI, Timer |
| TE-IP | TE0841 System-Controller |
| Application | Description |
|---|---|
| SREC SPI Bootloader | Bootloader for U-boot SREC. TE-Modified as library available. Used as Firmware for MicroBlaze. |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| MB Firmware | <firmware>/microblaze_0/ | MicroBlaze SREC SPI Bootloader Elf-File as firmware |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C, Flash, 2xDDR4 |
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Xilinx-IP | MicroBlaze, MB-Debug, Uartlite, 2x DDR4 SDRAM MIG, VIO |
| TE-IP | TE0841 System-Controller |
| Application | Description |
|---|---|
| memory_tests | Xilinx Memory Test |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Xilinx-IP | IBERT, MCU |
| TE-IP | SC0841, PRIM_STARTUP_U |
| Application | Description |
|---|---|
| SCU | System Controller Firmware for SI5338 initialisation (all outputs 125MHz). |
| Name | Folder | Description |
|---|---|---|
| SI5338 | misc/si5338 | Si5338 Clock Builder project |
| MCU Firmware | firmware/microblaze_mcs_0 | SCU Elf file for MCU |
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Xilinx-IP | MicroBlaze, MB-Debug, Uartlite,AXI Timer, AXI QSPI, 2x DDR4 SDRAM MIG |
| TE-IP | TE0841 System-Controller |
| Application | Description |
|---|---|
| memory_tests | Xilinx Memory Test |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO, Uart, 2x I2C, SD, Ethernet |
| IP Ethernet Lite | 2x Zynq GPIO to Ethernet |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO, Uart, 2x I2C, SD, Ethernet |
| IP Ethernet Lite | 2x Zynq GPIO to Ethernet |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated:I2C0, I2C1, UAR0, GPIO, SD0, USB0, ENET0, DDR3 |
| Xilinx-IP | AXI EthernetLite |
| Application | Description |
|---|---|
| hello_world | Xilinx default Hello World |
| u-boot | Petalinux-Uboot (image.ub on prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with 2x AXI Ethernet and I2C |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, I2C0, I2C1, UART0, UART1, GPIO, USB0, ETH0, DDR3 |
| Xilinx-IP | VIO, 2x AXI ETH Lite |
| TE-IP | STARTUPE2, Frequency Counter |
| Application | Description |
|---|---|
| zynq_fsbl | Xilinx default FSBL |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| Init Script | <design_name>/misc/sd_script/ | Init Script for ETH1 and ETH2 |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,ETH1,ETH2,SD,USB,RTC |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | activated: I2C0, UART0, GPIO, SD0, USB0, ENET0, QSPI |
| Application | Description |
|---|---|
| Zynq FSBL | Zynq FSBL (TE:modified) |
| hello_world | Xilinx Hello World Example |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | I2C0, UART0, GPIO, SD0, ETH0, USB0, QSPI |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for SI5338 Configuration (template in subfolder sw_lib) |
| ibert | Console output in endless loop |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| IBERT App. | <design_name>/sw_lib/ | Hello Application Template for SDK/HSI |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | I2C0, UART0, GPIO, SD0, ETH0, USB0, QSPI |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for SI5338 Configuration (template in subfolder sw_lib) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD1, I2C0, UART0, PCIe Gen2 1 Lane, Display Port, SATA 1 Lane |
| Xilinx-IP | VIO |
| TE-IP | TEBF0808 Base-Controller |
| Application | Description |
|---|---|
| hello_world.elf | Xilinx Hello World example |
| hello_te0803.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Modified FSBL, generated with SDK/HSI. (SDK Template:sw_lib/sw_apps) |
| bl31.elf | ATF generated with PetaLinux. |
| u-boot | Uboot generated with PetaLinux.(image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5338 | misc/Si5338 | Si5338ClockBuilder Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB, Ethernet, SATA, PCIe |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, UART0 |
| Application | Description |
|---|---|
| hello_te0803.elf | Hello TE0803 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD0, SD1, I2C0, UART0, PCIe Gen2 1 Lane, Display Port, SATA 1 Lane, DDR4 |
| Xilinx-IP | VIO |
| TE-IP | TEBF0808 Base-Controller, axis_live_audio_1.0 |
| Application | Description |
|---|---|
| hello_TE0803.elf | Hello TE0803 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Modified FSBL, generated with SDK/HSI. (SDK Template:sw_lib/sw_apps) |
| zynqmp_pmufw.elf | Default Xilinx PMU, generated with SDK/HSI. |
| bl31.elf | ATF generated with PetaLinux. |
| u-boot | Uboot generated with PetaLinux.(image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5345 | misc/Si5345 | ClockBuilder Pro Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB, Ethernet, SATA, PCIe, DisplayPort |
| Init Script | misc/init_script | Init Script for Audio |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, UART0, DDR4 |
| Application | Description |
|---|---|
| hello_TE0803.elf | Hello TE0803 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Xilinx default FSBL |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD1, CAN1, I2C0, UART0, PCIe-Lane 1, Display Port, SATA-Lane0 |
| Xilinx-IP | VIO,ILA |
| TE-IP | TEBF0808 Base-Controller, Labtools Frequency Counter, DisplayPort AUX Monitor |
| Application | Description |
|---|---|
| zynqmp_fsbl.elf | Modified FSBL, generated with PetaLinux-Project. |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with apps (early-init,fbv,si534x,spitool), bootloader(zynqmo_fsbl) and modules (clk-dummy). Additional Modifications: bootloader, system-top.dts, platform-top.h. Build steos: See /os/petalinux/readme.txt |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, Uart1, GPIO |
| Application | Description |
|---|---|
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with User-Application "disable_network" |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD1, CAN1, I2C0, UART0, PCIe-Lane 1, Display Port, SATA-Lane0 |
| Xilinx-IP | VIO,ILA |
| TE-IP | TEBF0808 Base-Controller, Labtools Frequency Counter, DisplayPort AUX Monitor |
| Application | Description |
|---|---|
| zynqmp_fsbl.elf | Modified FSBL, generated with PetaLinux-Project. |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with apps (early-init,fbv,si534x,spitool), bootloader(zynqmo_fsbl) and modules (clk-dummy). Additional Modifications: bootloader, system-top.dts, platform-top.h. Build steos: See /os/petalinux/readme.txt |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | SD1, QSPI, UART0, I2C |
| Xilinx-IP | IBERT Ultrascale GTH |
| Application | Description |
|---|---|
| zynqmp_fsbl | U+FSBL modified to initial SI534x PLL |
| hello_te0808 | Hello Te0808 as endless loop |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD1, I2C0, UART0, PCIe Gen2 1 Lane, Display Port, SATA 1 Lane |
| Xilinx-IP | VIO |
| TE-IP | TEBF0808 Base-Controller |
| Application | Description |
|---|---|
| hello_world.elf | Xilinx Hello World example |
| hello_te0808.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Modified FSBL, generated with SDK/HSI. (SDK Template:sw_lib/sw_apps) |
| bl31.elf | ATF generated with PetaLinux. |
| u-boot | Uboot generated with PetaLinux.(image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5345 | misc/Si5345 | ClockBuilder Pro Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB, Ethernet, SATA, PCIe |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, UART0 |
| Application | Description |
|---|---|
| hello_te0808.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD0, SD1, I2C0, UART0, PCIe Gen2 1 Lane, Display Port, SATA 1 Lane, DDR4(2400) |
| Xilinx-IP | VIO |
| TE-IP | TEBF0808 Base-Controller, axis_live_audio_1.0 |
| Application | Description |
|---|---|
| hello_te0808.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Modified FSBL, generated with SDK/HSI. (SDK Template:sw_lib/sw_apps) |
| zynqmp_pmufw.elf | Default Xilinx PMU, generated with SDK/HSI. |
| bl31.elf | ATF generated with PetaLinux. |
| u-boot | Uboot generated with PetaLinux.(image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5345 | misc/Si5345 | ClockBuilder Pro Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB, Ethernet, SATA, PCIe, DisplayPort |
| Debian SD-Image | <design_name>/prebuilt/os/debian/debian | Debian Image for SD-Card |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Debian SD-Image | *.img | Debian Image for SD-Card |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | GPIO, QSPI, GEM3, USB0, SD0, SD1, I2C0, UART0, PCIe Gen2 1 Lane, Display Port, SATA 1 Lane, DDR4 |
| Xilinx-IP | VIO |
| TE-IP | TEBF0808 Base-Controller, axis_live_audio_1.0 |
| Application | Description |
|---|---|
| hello_te0808.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Modified FSBL, generated with SDK/HSI. (SDK Template:sw_lib/sw_apps) |
| zynqmp_pmufw.elf | Default Xilinx PMU, generated with SDK/HSI. |
| bl31.elf | ATF generated with PetaLinux. |
| u-boot | Uboot generated with PetaLinux.(image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5345 | misc/Si5345 | ClockBuilder Pro Project |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with USB, Ethernet, SATA, PCIe, DisplayPort |
| Init Script | misc/init_script | Init Script for Audio |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, UART0, DDR4 |
| Application | Description |
|---|---|
| hello_te0808.elf | Hello TE0808 as endless loop with SDK/HSI.(SDK Template:sw_lib/sw_apps) |
| zynqmp_fsbl.elf | Xilinx default FSBL |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, GPIO,1x Uart,1x SPI,1x I2C |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated: SPI1, I2C0, UART1, QSPI, DDR3 |
| Application | Description |
|---|---|
| hello_world | Xilinx Hello World Example |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Zynq PS | activated MIO-Interfaces: DDR3, QSPI, GPIO, Uart, I2C, SD, Ethernet |
| Xilinx IPs | GMII to RGMII, VIO, RGMII Reset |
| TE IPs | TE0782 System Control |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | DDR3, QSPI, GPIO, Uart, I2C, SD, Ethernet |
| Xilinx IPs | GMII to RGMII, VIO, RGMII Reset |
| TE IPs | TE0782 System Control |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (TE::Modified) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| SI5338 SiLab Project | <design_name>/misc/si5338 | FSBL SI5338 configuration |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C, Flash, USB, Ethernet. Modified system-top.dts and platform-top.h. |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, I2C1, UART1, GPIO, SD1, USB0, USB1, ETH0, ETH1, DDR3 |
| Xilinx-IP | GMII to RGMII |
| TE-IP | TE0782 System Control |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for SI5338 Configuration (template in subfolder sw_lib) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with ETH0,RTH1,USB0,USB1,RTC |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Legacy device driver collection (DEWESoft) for Trenz Electronic FPGA modules equipped with FX2 USB microcontroller. Not recommended for new designs.
Please find here:
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please browse our current open software repositories:
Utility programs for restoring and updating firmware of Trenz Electronic USB FX2 FPGA modules.
System requirements:
Open_FUT (generation 2) source code hosted by
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please watch generation 2 to generation 3
Please find here:
Migration from the second generation (aka DEWESoft USB FX2) to the third generation (aka TE USB FX2) of Trenz Electronic USB FX2 technology stack (firmware, driver and APIs).
System requirements:Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please watch generation 2 to generation 3
Please find here:
Current device driver collection (Trenz Electronic) for Trenz Electronic FPGA modules equipped with FX2 USB microcontroller.
Please read the corresponding Trenz Electronic
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please read the corresponding Trenz Electronic
"FilesToImportForApplicationCpp" contains files required to create a new C++ software project that uses TE_USB_FX2_CyAPI.dll.
In particular, there are two header files: TE_USB_FX2_CyAPI.h and CyApi.h. This two files shall be added to the new C++ software project under "Include files".
The DLL32 subdirectory contains various files, but the only file necessary for a new C++ software project is TE_USB_FX2_CyAPI.dll that shall be added under "Resource Files". The other files have been stored here for completness.
The DLL64 subdirectory contains various files, but the only file necessary for a new C++ software project is TE_USB_FX2_CyAPI.dll that shall be added under "Resource Files". The other files have been stored here for completness.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI-32-VSExpress+VSProfessional contains the Microsoft Visual Studio 2010 Express C++ project with CyAPI.lib (for 32 bit) and settings adapted to compile under Visual Studio 2010 Express and Professional.
This software project creates TE_USB_FX2_CyAPI.dll for 32 bit.
The use of symbolic debugging is set to yes.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI-64-VSExpress contains the Microsoft Visual Studio 2010 Express C++ project with CyAPI.lib (for 64 bit) and settings adapted to compile under Microsoft Visual Studio 2010 Express C++.
This software project creates TE_USB_FX2_CyAPI.dll for 64 bit, under Visual Studio 2010 Express.
The use of symbolic debugging is set to yes.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI-64-VSProfessional contains the Visual Studio 2010 Express C++ project with CyAPI.lib (for 64 bit) and settings adapted to compile under Visual Studio 2010 Professional.
This software project creates TE_USB_FX2_CyAPI.dll for 64 bit, under Visual Studio 2010 Professional.
The use of symbolic debugging is set to yes.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI_SampleApplication-32-VSExpress+VSProfessional contains the Microsoft Visual Studio 2010 Express C++ project with TE_USB_FX2_CyAPI.dll (for 32 bit) and settings adapted to compile under Visual Studio 2010 Express and Professional.
The use of symbolic debugging is set to yes, and this can slow down the building process.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI_SampleApplication-64-VSExpress contains the Microsoft Visual Studio 2010 Express C++ project with TE_USB_FX2_CyAPI.dll (for 64 bit) and settings adapted to compile under Visual Studio 2010 Express.
The use of symbolic debugging is set to yes, and this can slow down the building process.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyAPI_SampleApplication-64-VSProfessional contains the Microsft Visual Studio 2010 Express C++ project with TE_USB_FX2_CyAPI.dll (for 64 bit) and settings adapted to compile under Visual Studio 2010 Professional.
The use of symbolic debugging is set to yes, and this can slow down the building process.
For further information, please read UM-TE_USB_API.cpp.pdf.
TE_USB_FX2_CyUSB contains the Microsoft Visual Studio 2010 Express C# project with CyUSB.dll and settings adapted to compile under Visual Studio 2010 Express and Professional for the creation of the TE_USB_FX2_CyUSB.dll API DLL.
Note: under Microsoft Visual Studio 2010 Express C# some settings are not selectable. In particular there is a "bug" that forces the compilation result into Debug folder even if Release is selected.
This problem does not exist under Visual Studio 2010 Professional, even if the project has been created using Express.
For further information, please read UM-TE_USB_API.cs.pdf.
TE_USB_FX2_CyUSB_SampleApplication contains the Microsoft Visual Studio 2010 Express C# project with TE_USB_FX2_CyUSB.dll and CyUSB.dll and settings adapted to compile under Visual Studio 2010 Express and Professional.
Note: under Microsoft Visual Studio 2010 Express C# some settings are not selectable. In particular there is a "bug" that forces the compilation result into Debug folder even if Release is selected.
This problem does not exist under Visual Studio 2010 Professional, even if the project has been created using Express.
For further information, please read UM-TE_USB_API.cs.pdf.
Please read the corresponding Trenz Electronic USB Suite Documentation.
Please browse our current open software repositories:
Programming tool to update or restore USB FX2 microcontroller firmware and FPGA bitsream on TE USB-based modules.
System requirements:
Source code
Programm to update FX2 and FPGA firmware on TE USB-based modules.
System requirements:
Source code
Programming tool to update or restore USB FX2 microcontroller firmware and FPGA bitsream on TE USB modules.
Linux version available
Programming tool to update or restore USB FX2 microcontroller firmware and FPGA bitsream on TE USB-based modules.
System requirements:
Source code
Please read the Trenz Electronic
System requirements:
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Please find here:
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
Note: it seems to work just with Cypress Control Center (.NET), not with Cypress CyConsole (C++)
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
YOu might have to disable driver signature enforcement.
Please visit
Please check your VID/PID in device manager (devmgmt.msc > properties > details > Hardware Ids).
You might have to disable driver signature enforcement.
Common documentation and device drivers repository for Trenz Electronic FPGA modules equipped with USB interface:
Current documentation is available
Please browse our current open software repositories:
Please browse our current open software repositories:
Please browse our current open software repositories:
| Component | Description |
|---|---|
| Zynq PL | DDR deactivated |
| Xilinx IPs | AXI GPIO, AXI Uart Lite |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader with modification for "DDR Less Zynq" |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated:I2C1,UART0,GPIO,SD0,QSPI |
| Xilinx-IP | AXI GPIO, AXI Uart Lite |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader with modification for "DDR Less Zynq" |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | activated:I2C1,UART0,GPIO,SD0,QSPI |
| Xilinx-IP | AXI GPIO, AXI Uart Lite |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader with modification for "DDR Less Zynq" |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | I2C1,UART0,GPIO,SD0,QSPI |
| Xilinx-IP | AXI GPIO, AXI Uart Lite |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for DDR less Zynq (template in subfolder sw_lib) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
Community contributions are provided "as is", without any express or implied warranty. Trenz Electronic encourages anyone to share and improve its EDA (electronic design automation) part library collection.
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI,2x Uart,I2C, SD,USB |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated: QSPI, I2C0 UART0, UART1, GPIO, SD1, USB0 |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example (ps7_uart_0 (JTAG USB)) |
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, I2C0, UART0, UART1, GPIO, SD1, USB0 |
| Application | Description |
|---|---|
| zynq_fsbl | default Xilinx FSBL |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with SD,USB |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI,Uart,I2C,SD,USB |
| HDMI System | Video to HDMI |
| IP RPI GPIO | Raspberry PI GPIO |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example (use ps7_uart_1 in SDK!) |
| display_test | HDMI test image activation and Uart message (use ps7_uart_1 in SDK!) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Zynq PS | activated MIO-Interfaces: I2C, Uart, SD, USB, Flash |
| TE-IPs | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, csi2_rx_phy, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0(Modified Xilinx IP) |
| Digilent IPs | axi_i2s_adi_1.2 |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified for VDMA) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (UN:root,PW:root) (image.ub in prebuilt-folder,ex.:/os/petalinux/TE0726-02M) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| Zynq Processor | activated MIO-Interfaces: DDR3, QSPI, Uart, I2C,SD |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader |
| hello_world | Xilinx Hello World Example (use ps7_uart_1 in SDK!) |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| Bit-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Hardware Specification from the vivado project. Used in SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated: I2C, Uart, SD, USB, Flash |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, csi2_rx_phy, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0(Modified Xilinx IP) |
| Digilent-IP | axi_i2s_adi_1.2 |
| XILINX-IP | AXI VDMA, AXI Strem Data Fifo, MMCM |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified for VDMA, fsbl_hooks.c camera frame buffer address selectable) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (UN:root,PW:root) (image.ub in prebuilt-folder,ex.:/os/petalinux/te0726_m) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| Camera Init-Script | <design_name>/misc/sd_init_script | Camera init.sh script for SD-Card |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | activated: I2C, Uart, SD, USB, Flash |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, csi2_rx_phy, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0(Modified Xilinx IP) |
| Digilent-IP | axi_i2s_adi_1.2 |
| XILINX-IP | AXI VDMA, AXI Strem Data Fifo, MMCM |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified for VDMA, fsbl_hooks.c camera frame buffer address selectable) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (UN:root,PW:root) (image.ub in prebuilt-folder,ex.:/os/petalinux/te0726_m) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| Debian Shell Script | <design_name>/os/petalinux | Script to generate Debian SD-Image(see readme.txt) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Debian SD-Image | *.img | Debian Image for SD-Card |
| Component | Description |
|---|---|
| PS-MIOs | activated: I2C, Uart, SD, USB, Flash |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, csi2_rx_phy, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0(Modified Xilinx IP) |
| Digilent-IP | axi_i2s_adi_1.2 |
| XILINX-IP | AXI VDMA, AXI Strem Data Fifo, MMCM |
| Application | Description |
|---|---|
| zynq_fsbl | Zynq First Stage Bootloader (Modified for VDMA, fsbl_hooks.c camera frame buffer address selectable) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (UN:root,PW:root) (image.ub in prebuilt-folder,ex.:/os/petalinux/te0726_m) |
| Name | Folder | Description |
|---|---|---|
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| FFMPEG | <design_name>/misc/ffmpeg | Files for SD |
| mplayer | <design_name>/misc/mplayer | Files for SD |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Component | Description |
|---|---|
| PS-MIOs | active:QSPI, USB0, SD0, SD1, UART0, UART1, I2C0, I2C1, SPI0, SPI1, GPIO |
| TE-IP | pinmux control (Beta), rpi_gpio_v1_0 (Beta) |
| Application | Description |
|---|---|
| Hello TE0726 | Hello ZynqBerry Console Example Hello ZynqBerry Console Example (print output as loop) |
| u-boot | Petalinux-Uboot (image.ub in prebuilt-folder,ex.:/os/petalinux/default) |
| Name | Folder | Description |
|---|---|---|
| Source Name | <design_name><folder> | Source Description |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Projekt (RPI-GPIO-IP modification: system-top.dts (uart alias for correct uart usage), platform-top.h (U-Boot settings for sd usage) ) |
| File | File-Extension | Description |
|---|---|---|
| Bin-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| BIF-File | *.bif | File with description to generate Bin-File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Diverse Reports | -- | Report files in different formats |
| Komponente | Beschreibung |
|---|---|
| PS-MIOs | QSPI, DDR, I2C1, UART1, GPIO, SD1, USB0 |
| Anwendung | Beschreibung |
|---|---|
| zynq_fsbl | Default Xilinx FSBL |
| hello_te0726 | Hello TE0726 as endless loop (template in sobfolder sw_lib) |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Ordner | Beschreibung |
|---|---|---|
| hello_te0726 | <design_name>/sw_lib/ | Modified Hello World Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Projekt mit SD,USB, ETH over USB |
| Dateien | Datei-Endung | Beschreibung |
|---|---|---|
| BIF-File | *.bif | Datei mit Beschreibung für die Bin-File Generierung |
| BIN-File | *.bin | Flash Konfigurationsdatei mit Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Konfigurationsdatei |
| Diverse Reports | --- | Report-Dateien in verschiedenen Formaten |
| Hardware-Platform-Specification-Files | *.hdf | Exportierte Vivado Hardware Specification für SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Projekt Datei |
| OS-Image | *.ub | Image mit Linux Kernel (enthält für Petalinux optional auch Devicetree und RAM-Disk) |
| Software-Application-File | *.elf | Software Anwendung für Zynq oder MicroBlaze Processor Systeme |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, DDR3, I2C0, I2C1, UART1, GPIO, SD1, USB0 |
| Xilinx-IP | AXI Stream Fifo,AXI VDMA, MMCM |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_to_i2s_1.0, axis_video_dwidth_converter_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0 |
| Digilent-IP | axi_i2s_adi_1.2 |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for Frame Buffer Address |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH,SD,USB |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| Camera Init-Script | <design_name>/misc/img | Camera init.sh script for SD-Card |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, DDR3, I2C0, I2C1, UART1, GPIO, SD1, USB0 |
| Xilinx-IP | AXI Stream Fifo,AXI VDMA, MMCM |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_to_i2s_1.0, axis_video_dwidth_converter_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0 |
| Digilent-IP | axi_i2s_adi_1.2 |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for Frame Buffer Address |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH,SD,USB and script to generate debian image |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| Debian SD-Image | <design_name>/prebuilt/os/debian/debian | Debian Image for SD-Card |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Debian SD-Image | *.img | Debian Image for SD-Card |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, DDR3, I2C0, I2C1, UART1, GPIO, SD1, USB0 |
| Xilinx-IP | AXI Stream Fifo,AXI VDMA, MMCM |
| TE-IP | axi_reg32_1.0,axis_audio_pwm_1.0, axis_fb_conv_1.0, axis_raw_demosaic_1.0, axis_raw_unpack_1.0, axis_to_i2s_1.0, axis_video_dwidth_converter_1.0, axis_video_resize_1.0, csi_to_axis_1.0, csi2_d_phy_rx_1.0, i2s_to_pwm_1.0, Video_IO_2_HDMI_TMDS_1.0 |
| Digilent-IP | axi_i2s_adi_1.2 |
| Application | Description |
|---|---|
| zynq_fsbl | TE modified Zynq FSBL for Frame Buffer Address |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH,SD,USB |
| RGBA Images Converter | <design_name>/misc/img | Python Script+Batch File, as well as RGBA and PNG files |
| Camera Init-Script | <design_name>/misc/img | Camera init.sh script for SD-Card |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, GEM3(Ethernet), USB0, SD0, SD1, I2C0, UART0, PCIe, Display Port, DDR4 SoDIMM(4Gb,1 Rank (KVR21S15S8/4)) |
| Xilinx-IP | VIO |
| TE-IP | labtools_fmeter |
| Application | Description |
|---|---|
| zynqmp_fsbl | TE modified Zynq FSBL for SI5338 and SI5345 Configuration (template in subfolder sw_lib) |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| SI5345 Project | <design_name>/misc/si5345/ | Clock Builder Pro Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB,PCIe |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| PS-MIOs | QSPI, GEM3(Ethernet), USB0, SD0, SD1, I2C0, UART0, PCIe, Display Port, DDR4 SoDIMM(4Gb,1 Rank (KVR24S17S8/8)) |
| Xilinx-IP | VIO |
| TE-IP | labtools_fmeter |
| Application | Description |
|---|---|
| zynqmp_fsbl | TE modified Zynq FSBL for SI5338 and SI5345 Configuration (template in subfolder sw_lib) |
| hello_world | Xilinx Hello World Example |
| u-boot | Petalinux-Uboot (image.ub in <design_name>/prebuilt/os/petalinux/<short dir or default>) |
| Name | Folder | Description |
|---|---|---|
| SI5338 Project | <design_name>/misc/si5338/ | Clock Builder Desktop Project, with all CLKs enabled. |
| SI5345 Project | <design_name>/misc/si5345/ | Clock Builder Pro Project, with all CLKs enabled. |
| FSBL Template | <design_name>/sw_lib/ | Modified FSBL Template for SDK/HSI |
| PetaLinux Project | <design_name>/os/petalinux | PetaLinux Project with I2C,ETH0,SD,USB,PCIe |
| File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
| Component | Description |
|---|---|
| Xilinx-IP | VIO |
| TE-IP | PRIM_STARTUP, labtools_fmeter |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| Component | Description |
|---|---|
| Xilinx-IP | MicroBlaze, MMCM, AXI INTC, AXI Timer, AXI I2C, AXI MM to PCIe, AXI QSPI, VIO |
| Application | Description |
|---|
| Name | Folder | Description |
|---|
| File | File-Extension | Description |
|---|---|---|
| BIT-File | *.bit | FPGA Configuration File |
| DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
| MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
