Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board - academic

Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board - academic

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Product information "Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board - academic"

Sale of academic articles only within Germany and Austria.

The Genesys ZU-5EV is designed with high-definition video in mind, and is ideal for multimedia, automotive ADAS, surveillance, and other embedded vision applications. The board features a Xilinx Zynq® UltraScale+™ MPSoC (Multi-Processing System on Chip) EV device.

The ZU5EV is equipped with a quad-core Arm® Cortex®-A53 applications processor, dual-core Cortex-R5 real-time processor, Mali™-400 MP2 graphics processing unit, 4KP60 capable H.264/H.265 video codec, and 16nm FinFET+ programmable logic. The excellent mix of on-board peripherals, upgrade-friendly DDR4, Mini PCIe and microSD slots, multi-camera, a video codec, and GTH transceivers allowing HDMI Source, Sink and 10G SFP+ to support a wide number of use-cases.

Different specialized ports, including FMC Gigabit expansion ports, Pmod and high-speed SYZYGY-compliant expansion module ports for our new Zmods, enable flexible expansion and easy access to a wide ecosystem of add-on modules, perfect for silicon evaluation and rapid prototyping.

Digilent products are warranted to be free from manufacturing defects for 30 days from the date of purchase. No other express or implied warranties are provided.

Features

XCZU5EV-SFVC784-1-E (with heat sink and fan)
- Quad-core ARM® Cortex-A53 Application Processing Unit
- Dual-core ARM® Cortex-R5 Real-Time Processing Unit
- Mali-400 MP2 graphics processing unit
- 256K logic cells
Memory:
- 4 GiB DDR4 SODIMM module
- ISSI 256 MB SNOR Flash
- MicroSD Card Slot
Peripheral connectivity:
- USB Type-C 3.1 Gen1 Dual-Role Device
- MiniPCIe / mSATA dual slot
- USB 2.0 Host
Network connectivity:
- 2.4 GHz on-board WiFi
- 1G w/IEEE 1588 Ethernet
- SIM card slot
- WLAN/WWAN/LoRa: option - MiniPCIe
- SFP+ 10G Ethernet
Multimedia:
- 1.2a Dual-Lane Display Port
- 2 x Pcam Dual-Lane
- Audio Codec
- H.264/H.265
- HDMI Source
- HDMI Sink
Expansion:
- 1 x FMC expansion connector
- 1 x FMC Gigabit
- 1 x SYZYGY port
- 4 x Pmod ports
GPIO: LED, Buttons, Switches

Target Applications

Situational Awareness
Surveillance/Reconnaissance
Smart Vision
Image Manipulation
Graphic Overlay
Human Machine Interface
Automotive ADAS
Video Processing
Interactive Display

Project Links

Installing Vivado, Xilinx SDK and Digilent Board Files
- Note: When installing Vivado, make sure to include support for Zynq Ultrascale+ parts.
- Note: Digilent projects for the Genesys ZU are currently only supported in Vivado 2019.1.
Getting Started with Vivado IP Integrator
- Note: This guide was originally written for non-Ultrascale Zynq boards and boards using Microblaze. The flow for Ultrascale Zynq is largely the same as non-Ultrascale Zynq. The “Zynq Ultrascale+ MPSoC” IP core should be used in place of the “ZYNQ7 Processing System”.
Getting Started with the Genesys ZU
Genesys ZU Out-of-Box Vivado Project
Genesys ZU Out-of-Box Petalinux Project
Genesys ZU 5EV HDMI Demo Project

Scope of Delivery

1 x Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board
Power Supply, Desktop, 12V, 8A, w/PCIE Connector
IEC cable, EU, 1.2 meter
USB A TO MICRO B CABLE
Cable, USB, A to Type C, 15 cm
JTAG HS1
Voucher for the Xilinx MIPI CSI-2 IP cores

References

Manufacturer: Digilent Inc.
Manufacturer's article name: Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board
Manufacturer's article number: 410-383-5EV

Resources

Other Digilent products are available on request.

Please note:

Articles with academic pricing may be sold by us only within Germany and Austria. If you are located in following countries, please order from your local distributor.

Academic articles are technically identical to their corresponding non-academic article.

In order to process an academic order, these documents are strictly required:

an official order by school/university/eligible institution
OR
a copy or scan of the matriculation certificate as well as the university email address of the student

No academic order will be accepted and processed if these documents are missing.

These data will be transmitted in the course of proper fulfillment of the contractual purpose (General Data Protection Regulation, chapter 6 sentence 1 b) to the manufacturer of this article:
Digilent, Inc.
P.O. Box 428 Pullman
WA 99163-0428.

If you do not agree to the transfer of data, there is no possibility to order this article with academic pricing. Furthermore, you are entitled at any time to request comprehensive information on the data stored about your person. You can also request the correction, deletion and blocking of individual personal data at any time.

Please send us the data by e-mail to sales@trenz-electronic.de after ordering.

Related links to "Genesys ZU-5EV: Zynq Ultrascale+ MPSoC Development Board - academic"

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

File	File-Extension	Description
Bin-File	*.bin	Flash Configuration File with Boot-Image for Zynq-FPGAs
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlace Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
BIF-File	*.bif	File with description to generate Bin-File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Diverse Reports	--	Report files in different formats