MPSoC Module with AMD Zynq™ UltraScale+™ 3CG-L1I, 1 GByte LPDDR4, 4 x 5 cm, LP

MPSoC Module with AMD Zynq™ UltraScale+™ 3CG-L1I, 1 GByte LPDDR4, 4 x 5 cm, LP

€619.00 (736.61 € gross) *

Prices plus VAT plus shipping costs

Possible to order, delivery time on request.

Order number: TE0823-01-3PIU1ML
In Stock: 0
Article status: Full production

Quantity	Unit price
To 9	€619.00 (736.61 € gross) *
From 10	€557.10 (662.95 € gross) *
From 25	€557.10 (662.95 € gross) *
From 50	€495.20 (589.29 € gross) *
From 100	€464.25 (552.46 € gross) *
From 250	€464.25 (552.46 € gross) *
From 500	€414.73 (493.53 € gross) *
From 1000	€414.73 (493.53 € gross) *

This product is not always in stock, but will be produced on customer order (on demand).... more

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Product information "MPSoC Module with AMD Zynq™ UltraScale+™ 3CG-L1I, 1 GByte LPDDR4, 4 x 5 cm, LP"

This product is not always in stock, but will be produced on customer order (on demand).
Please ask for any minimum quantities.

The predecessor of this article is TE0823-01-3PIU1FL. All changes are in the Product Change Notification (PCN).

This module is identical to variant TE0823-01-3PIU1MA except the lower 2.5 mm Samtec connectors.

The Trenz Electronic TE0823-01-3PIU1ML is an industrial-grade MPSoC module integrating a low power AMD/Xilinx Zynq™ UltraScale+™ ZU3CG, 1 GByte LPDDR4 SDRAM, 128 MByte Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

All this on a tiny footprint, smaller than a credit card, at the most competitive price. Modules in 4 x 5 cm form factor are fully mechanically and largely electrically compatible among each other.

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Key Features

General

Rugged for shock and high vibration
Evenly spread supply pins for good signal integrity
Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)

SoC/FPGA

AMD/Xilinx Zynq™ UltraScale+™ XCZU3CG-L1SFVC784I (Low Power)
- Application Processor: Dual-core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
Package: SFVC784
Device: ZU3
Engine: CG
Speed: -1LI (also non-low power assembly options possible)
Temperature range: industrial

RAM/Storage

Low power DDR4 on PS with 32 bit data width
128 MByte QSPI boot Flash in dual parallel mode
8 GByte e.MMC memory with 8 bit data width
MAC address serial EEPROM with EUI-48 node identity

On Board

Lattice LCMXO2
PLL SI5338
Gigabit Ethernet transceiver PHY
Hi-speed USB2 ULPI transceiver with full OTG support

Interface

132 x HP PL I/Os (3 banks)
ETH
USB
4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
- PCI Express interface version 2.1 compliant
- SATA 3.1 specification compliant interface
- DisplayPort source-only interface with video resolution up to 4k x 2k
- USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
- 1 GB/s serial GMII interface
14 x PS MIOs
- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
JTAG
Ctrl

Power

3.3V-5V main input
3.3V controller input
Variable bank I/O power input
All power supplies on board

Dimension

4 x 5 cm form factor

Other assembly options for cost or performance optimization plus high volume prices available on request.

Recommended Software

Vivado ML Enterprise Edition

Development Support

There are different base boards available for this module.

Latest documentation, design support files and reference designs with source files are available for download free of charge.

Applications

Sensor Processing & Fusion
Motor Control
Low-cost Ultrasound
Traffic Engineering

Scope of Delivery

1 x TE0823-01-3PIU1ML Trenz Electronic MPSoC module with AMD/Xilinx Zynq™ UltraScale+™ ZU3CG (low power) and low profile socket strips

Additional Information

Manufacturer's article number: TE0823-01-3PIU1ML
Trenz Electronic TE0823 Wiki
Samtec LSHM Razor Beam, High-Speed Hermaphroditic Terminal/Socket Strips, low profile 2.5 mm,
information concerning mating heights: Wiki, mounted on every 4 x 5 cm module from us marked with "LP" or "low profile".
Support Forum

All modules produced by Trenz Electronic are developed and manufactured in Germany.

Related links to "MPSoC Module with AMD Zynq™ UltraScale+™ 3CG-L1I, 1 GByte LPDDR4, 4 x 5 cm, LP"

Downloads

File	File-Extension	Description
Bit-File	*.bit	FPGA Configuration File
Diverse Reports	--	Report files in different formats

Component	Description
IP-Interfaces	I2C, ASIO (AXI-Stream to IO), SPI-Flash, Uart

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	I2C,SPI-Flash,UART
TE-IP	ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO
TE-IP	Startupe2,LabTools Frequency Counter

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Xilinx-IP	VIO (Virtual Input/Output)
TE-IP	Labtools Frequency Counter, Startupe2 Primitive Wrapper

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
Reference Design	Reference Designs sort by ISE/EDK Version
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Directory	Content
PCN	Product change notifications: Important changes between hardware revisions
REV0x	Documents and source files sorted by PCB revision. Connector Pinout Viewer/XDC-Generator available on TE Master Pinout, as well as a additional informations on All Trenz Electronic SoMs
	Documents	PDF documents, like Technical Reference Manual, Schematics, Assembly Diagrams and...
	Firmware	Initial configuration for diverse PCB components, like CPLD, PLL and ...
	HW Design	Relevant files for PCB-Design, like PCB-STEP-Model, Cooler-STEP-Model, Trace-length, Altium libraries / projects (only for selected carrier boards), and ...
	Pictures	PCB-Pictures

Component	Description
Interface IPs	DDR3, GPIO, Uart0, QSPI and Ethernet

Application	Description
hello_world	Xilinx Hello World Example (.elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	MicroBlaze, MB-Debug, Uartlite, MIG7 for DDR3, QSPI, Timer, Ethernet Lite
TE-IP	ASIO GPIO (AXI-Stream to GPIO)

Application	Description
Hello World	Xilinx Hello world ( generate elf file only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	VIO,ILA
TE-IP	unio_mac

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File

Component	Description
Interface IPs	QSPI, Uart, ASIO (Axi-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	ILA, VIO, CLK-Wizard
TE-IP	F32C, Vector_LED, UART_MON

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

Component	Description
IP-Interfaces	DDR3, QSPI, Uart, I2C, Ethernet, ASIO (AXI-Stream to IO)

Application	Description
hello_world	Xilinx Hello World Example (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
Bit-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Hardware Specification from the vivado project. Used in SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite, VIO
TE-IP	ASIO (AXI-Stream to IO), labtools_fmeter

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
te_spi_bootloader	SPI Bootloader (.elf only)

File	File-Extension	Description
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
BIT-File	*.bit	FPGA Configuration File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Diverse Reports	--	Report files in different formats

Component	Description
Xilinx-IP	AXI Timer, AXI Interrupt Controller,MIG, AXI QSPI, AXI Uart Lite, AXI I2C, AXI Ethernet Lite

Application	Description
hello_world	Xilinx Hello World Example (.elf only)
memory_tests	Xilinx Memory Example (.elf only)

File	File-Extension	Description
BIT-File	*.bit	FPGA Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Component	Description
Zynq Processor	activated MIO-Interfaces: DDR3, QSPI, GPIO,2x Uart, QSPI,2x I2C,2x SD,1x Ethernet

Application	Description
zynq_fsbl	Zynq First Stage Bootloader (for hdmi modified and provided as library in /sw_lib/)
hello_world	Xilinx Hello World Example

Digilent
OHO-Elektronik
Sundance
Trenz_Electronic - Documents and Design files for Trenz Electronic Products
inrevium
reference

Name	Folder	Description
Source Name	<design_name><folder>	Source Description
PetaLinux Project	<design_name>/os/petalinux	PetaLinux Project with Ethernet,USB,RTC

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